
Christine Trinh Le Tu
Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784 |
| Total Applications | 1748 |
| Issued Applications | 1571 |
| Pending Applications | 27 |
| Abandoned Applications | 152 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11097444
[patent_doc_number] => 20160294413
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-10-06
[patent_title] => 'METHODS AND APPARATUS FOR EMBEDDING AN ERROR CORRECTION CODE IN MEMORY CELLS'
[patent_app_type] => utility
[patent_app_number] => 14/675294
[patent_app_country] => US
[patent_app_date] => 2015-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 10937
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14675294
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/675294 | Methods and apparatus for embedding an error correction code in memory cells | Mar 30, 2015 | Issued |
Array
(
[id] => 11232731
[patent_doc_number] => 09459959
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-10-04
[patent_title] => 'Failure-decoupled volume-level redundancy coding techniques'
[patent_app_type] => utility
[patent_app_number] => 14/673796
[patent_app_country] => US
[patent_app_date] => 2015-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 15572
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14673796
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/673796 | Failure-decoupled volume-level redundancy coding techniques | Mar 29, 2015 | Issued |
Array
(
[id] => 12395682
[patent_doc_number] => 09966146
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-05-08
[patent_title] => Memory system and method of controlling non-volatile memory
[patent_app_type] => utility
[patent_app_number] => 14/636321
[patent_app_country] => US
[patent_app_date] => 2015-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3913
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14636321
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/636321 | Memory system and method of controlling non-volatile memory | Mar 2, 2015 | Issued |
Array
(
[id] => 10284400
[patent_doc_number] => 20150169399
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-18
[patent_title] => 'DRAM ADDRESS PROTECTION'
[patent_app_type] => utility
[patent_app_number] => 14/629770
[patent_app_country] => US
[patent_app_date] => 2015-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3877
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14629770
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/629770 | DRAM address protection | Feb 23, 2015 | Issued |
Array
(
[id] => 10276007
[patent_doc_number] => 20150161003
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-11
[patent_title] => 'STORAGE SYSTEM AND STORAGE CONTROL APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 14/623028
[patent_app_country] => US
[patent_app_date] => 2015-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 93
[patent_figures_cnt] => 93
[patent_no_of_words] => 34608
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14623028
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/623028 | Storage system and storage control apparatus | Feb 15, 2015 | Issued |
Array
(
[id] => 10538434
[patent_doc_number] => 09264075
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-02-16
[patent_title] => 'Dynamic buffer partitioning'
[patent_app_type] => utility
[patent_app_number] => 14/621412
[patent_app_country] => US
[patent_app_date] => 2015-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4398
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14621412
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/621412 | Dynamic buffer partitioning | Feb 12, 2015 | Issued |
Array
(
[id] => 10335377
[patent_doc_number] => 20150220383
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-08-06
[patent_title] => 'RECEPTION CIRCUIT OF IMAGE DATA, ELECTRONIC DEVICE USING THE SAME, AND METHOD OF TRANSMITTING IMAGE DATA'
[patent_app_type] => utility
[patent_app_number] => 14/609903
[patent_app_country] => US
[patent_app_date] => 2015-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5221
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14609903
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/609903 | Reception circuit of image data, electronic device using the same, and method of transmitting image data | Jan 29, 2015 | Issued |
Array
(
[id] => 10250033
[patent_doc_number] => 20150135029
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-05-14
[patent_title] => 'TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS'
[patent_app_type] => utility
[patent_app_number] => 14/605329
[patent_app_country] => US
[patent_app_date] => 2015-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6020
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14605329
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/605329 | TDO multiplexers series coupling augmentation instruction register with instruction registers | Jan 25, 2015 | Issued |
Array
(
[id] => 10228368
[patent_doc_number] => 20150113361
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-23
[patent_title] => 'APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING A QUASI-CYCLIC LOW DENSITY PARITY CHECK CODE IN A MULTIMEDIA COMMUNICATION SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 14/579146
[patent_app_country] => US
[patent_app_date] => 2014-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 32111
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14579146
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/579146 | Apparatus and method for transmitting and receiving a quasi-cyclic low density parity check code in a multimedia communication system | Dec 21, 2014 | Issued |
Array
(
[id] => 10098072
[patent_doc_number] => 09134378
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-09-15
[patent_title] => 'Linear decompressor with two-step dynamic encoding'
[patent_app_type] => utility
[patent_app_number] => 14/572425
[patent_app_country] => US
[patent_app_date] => 2014-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 31
[patent_no_of_words] => 18367
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14572425
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/572425 | Linear decompressor with two-step dynamic encoding | Dec 15, 2014 | Issued |
Array
(
[id] => 10650478
[patent_doc_number] => 09366724
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-06-14
[patent_title] => 'Scan testing with staggered clocks'
[patent_app_type] => utility
[patent_app_number] => 14/566823
[patent_app_country] => US
[patent_app_date] => 2014-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 7697
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14566823
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/566823 | Scan testing with staggered clocks | Dec 10, 2014 | Issued |
Array
(
[id] => 11700011
[patent_doc_number] => 09689919
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-06-27
[patent_title] => 'Method and apparatus for testing memory'
[patent_app_type] => utility
[patent_app_number] => 14/556228
[patent_app_country] => US
[patent_app_date] => 2014-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3190
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14556228
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/556228 | Method and apparatus for testing memory | Nov 29, 2014 | Issued |
Array
(
[id] => 10270061
[patent_doc_number] => 20150155058
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-04
[patent_title] => 'ERROR CORRECTION CODE UNIT, SELF-TEST METHOD AND ASSOCIATED CONTROLLER APPLIED TO FLASH MEMORY DEVICE FOR GENERATING SOFT INFORMATION'
[patent_app_type] => utility
[patent_app_number] => 14/551060
[patent_app_country] => US
[patent_app_date] => 2014-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4500
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14551060
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/551060 | Error correction code unit, self-test method and associated controller applied to flash memory device for generating soft information | Nov 22, 2014 | Issued |
Array
(
[id] => 10802550
[patent_doc_number] => 20160148707
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-26
[patent_title] => 'Computer System Predicting Memory Failure'
[patent_app_type] => utility
[patent_app_number] => 14/549979
[patent_app_country] => US
[patent_app_date] => 2014-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5707
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14549979
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/549979 | Computer system predicting memory failure | Nov 20, 2014 | Issued |
Array
(
[id] => 10785548
[patent_doc_number] => 20160131704
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-12
[patent_title] => 'SCAN THROUGHPUT ENHANCEMENT IN SCAN TESTING OF A DEVICE-UNDER-TEST'
[patent_app_type] => utility
[patent_app_number] => 14/539555
[patent_app_country] => US
[patent_app_date] => 2014-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 9570
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14539555
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/539555 | Scan throughput enhancement in scan testing of a device-under-test | Nov 11, 2014 | Issued |
Array
(
[id] => 11482036
[patent_doc_number] => 09588578
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-03-07
[patent_title] => 'Method of changing an operating frequency for performing a dynamic voltage and frequency scaling, system on-chip, and mobile device having the same'
[patent_app_type] => utility
[patent_app_number] => 14/532649
[patent_app_country] => US
[patent_app_date] => 2014-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 23
[patent_no_of_words] => 14754
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14532649
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/532649 | Method of changing an operating frequency for performing a dynamic voltage and frequency scaling, system on-chip, and mobile device having the same | Nov 3, 2014 | Issued |
Array
(
[id] => 10078364
[patent_doc_number] => 09116208
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-08-25
[patent_title] => 'Address and command port with tap and master controller circuitry'
[patent_app_type] => utility
[patent_app_number] => 14/531459
[patent_app_country] => US
[patent_app_date] => 2014-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 81
[patent_figures_cnt] => 114
[patent_no_of_words] => 41616
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14531459
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/531459 | Address and command port with tap and master controller circuitry | Nov 2, 2014 | Issued |
Array
(
[id] => 10284335
[patent_doc_number] => 20150169333
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-18
[patent_title] => 'MEMORY DEVICE AND COMPUTING SYSTEM INCLUDING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/530951
[patent_app_country] => US
[patent_app_date] => 2014-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 11218
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14530951
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/530951 | Memory device and computing system including the same | Nov 2, 2014 | Issued |
Array
(
[id] => 10777887
[patent_doc_number] => 20160124043
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-05
[patent_title] => 'CIRCUIT TECHNIQUES FOR EFFICIENT SCAN HOLD PATH DESIGN'
[patent_app_type] => utility
[patent_app_number] => 14/528554
[patent_app_country] => US
[patent_app_date] => 2014-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8116
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14528554
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/528554 | Circuit techniques for efficient scan hold path design | Oct 29, 2014 | Issued |
Array
(
[id] => 9919293
[patent_doc_number] => 20150074498
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-03-12
[patent_title] => 'APPARATUSES AND METHODS FOR COMBINING ERROR CODING AND MODULATION SCHEMES'
[patent_app_type] => utility
[patent_app_number] => 14/525602
[patent_app_country] => US
[patent_app_date] => 2014-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4384
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14525602
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/525602 | Apparatuses and methods for combining error coding and modulation schemes | Oct 27, 2014 | Issued |