Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10910863 [patent_doc_number] => 20140313879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-23 [patent_title] => 'Processing Transport Packets' [patent_app_type] => utility [patent_app_number] => 14/321517 [patent_app_country] => US [patent_app_date] => 2014-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7844 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14321517 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/321517
Processing transport packets Jun 30, 2014 Issued
Array ( [id] => 10496184 [patent_doc_number] => 20150381206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'MULTI-STAGE DECODER' [patent_app_type] => utility [patent_app_number] => 14/319480 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13466 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14319480 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/319480
Multi-stage decoder Jun 29, 2014 Issued
Array ( [id] => 11208639 [patent_doc_number] => 09438274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Data processing block and data storage device including the same' [patent_app_type] => utility [patent_app_number] => 14/316436 [patent_app_country] => US [patent_app_date] => 2014-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5526 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14316436 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/316436
Data processing block and data storage device including the same Jun 25, 2014 Issued
Array ( [id] => 11346110 [patent_doc_number] => 09530523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Thermal disturb as heater in cross-point memory' [patent_app_type] => utility [patent_app_number] => 14/314200 [patent_app_country] => US [patent_app_date] => 2014-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8186 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14314200 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/314200
Thermal disturb as heater in cross-point memory Jun 24, 2014 Issued
Array ( [id] => 10509009 [patent_doc_number] => 09236888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-12 [patent_title] => 'Storage device, memory controller and memory control method' [patent_app_type] => utility [patent_app_number] => 14/306462 [patent_app_country] => US [patent_app_date] => 2014-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8388 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14306462 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/306462
Storage device, memory controller and memory control method Jun 16, 2014 Issued
Array ( [id] => 10643661 [patent_doc_number] => 09360524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'Testing system for serial interface' [patent_app_type] => utility [patent_app_number] => 14/305188 [patent_app_country] => US [patent_app_date] => 2014-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1209 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14305188 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/305188
Testing system for serial interface Jun 15, 2014 Issued
Array ( [id] => 10969793 [patent_doc_number] => 20140372826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-18 [patent_title] => 'APPARATUSES AND METHODS FOR ENCODING AND DECODING OF PARITY CHECK CODES' [patent_app_type] => utility [patent_app_number] => 14/303856 [patent_app_country] => US [patent_app_date] => 2014-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 19133 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14303856 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/303856
Apparatuses and methods for encoding and decoding of parity check codes Jun 12, 2014 Issued
Array ( [id] => 9758877 [patent_doc_number] => 20140289577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT' [patent_app_type] => utility [patent_app_number] => 14/297051 [patent_app_country] => US [patent_app_date] => 2014-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 82 [patent_figures_cnt] => 82 [patent_no_of_words] => 41414 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14297051 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/297051
Controller circuitry with state machines, address store/compare, and shift register Jun 4, 2014 Issued
Array ( [id] => 10962805 [patent_doc_number] => 20140365835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-11 [patent_title] => 'Receiver Bit Alignment for Multi-Lane Asynchronous High-Speed Data Interface' [patent_app_type] => utility [patent_app_number] => 14/293570 [patent_app_country] => US [patent_app_date] => 2014-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3342 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14293570 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/293570
Receiver bit alignment for multi-lane asynchronous high-speed data interface Jun 1, 2014 Issued
Array ( [id] => 11430985 [patent_doc_number] => 09569302 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-14 [patent_title] => 'Decoding of turbo product codes using miscorrection detection' [patent_app_type] => utility [patent_app_number] => 14/288777 [patent_app_country] => US [patent_app_date] => 2014-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6123 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14288777 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/288777
Decoding of turbo product codes using miscorrection detection May 27, 2014 Issued
Array ( [id] => 10956362 [patent_doc_number] => 20140359384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-04 [patent_title] => 'COMMUNICATION DEVICE, TEST SYSTEM AND TEST METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/285023 [patent_app_country] => US [patent_app_date] => 2014-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6141 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14285023 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/285023
Communication device, test system and test method thereof May 21, 2014 Issued
Array ( [id] => 10446734 [patent_doc_number] => 20150331748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-19 [patent_title] => 'METHOD TO DYNAMICALLY UPDATE LLRs IN AN SSD DRIVE AND/OR CONTROLLER' [patent_app_type] => utility [patent_app_number] => 14/280884 [patent_app_country] => US [patent_app_date] => 2014-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5404 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14280884 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/280884
Method to dynamically update LLRs in an SSD drive and/or controller May 18, 2014 Issued
Array ( [id] => 10264877 [patent_doc_number] => 20150149874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'RELIABILITY METRIC FOR DECODING HYPOTHESIS' [patent_app_type] => utility [patent_app_number] => 14/274266 [patent_app_country] => US [patent_app_date] => 2014-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12690 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14274266 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/274266
Reliability metric for decoding hypothesis May 8, 2014 Issued
Array ( [id] => 10934661 [patent_doc_number] => 20140337682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'Multiple size and rate FEC code combination with minimum shortening and maximum combined code rate' [patent_app_type] => utility [patent_app_number] => 14/273264 [patent_app_country] => US [patent_app_date] => 2014-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13600 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273264 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/273264
Multiple size and rate FEC code combination with minimum shortening and maximum combined code rate May 7, 2014 Issued
Array ( [id] => 10264845 [patent_doc_number] => 20150149842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'TEST DEVICE AND METHOD USING A SEPARATE CONTROL MODULE FOR TEST' [patent_app_type] => utility [patent_app_number] => 14/244449 [patent_app_country] => US [patent_app_date] => 2014-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3520 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14244449 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/244449
TEST DEVICE AND METHOD USING A SEPARATE CONTROL MODULE FOR TEST Apr 2, 2014 Abandoned
Array ( [id] => 15077247 [patent_doc_number] => 10468118 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => DRAM row sparing [patent_app_type] => utility [patent_app_number] => 15/115971 [patent_app_country] => US [patent_app_date] => 2014-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10939 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15115971 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/115971
DRAM row sparing Mar 2, 2014 Issued
Array ( [id] => 9563895 [patent_doc_number] => 20140181608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS' [patent_app_type] => utility [patent_app_number] => 14/190314 [patent_app_country] => US [patent_app_date] => 2014-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6004 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14190314 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/190314
IC test linking module with augmentation instruction shift register Feb 25, 2014 Issued
Array ( [id] => 9673448 [patent_doc_number] => 20140237311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS' [patent_app_type] => utility [patent_app_number] => 14/189387 [patent_app_country] => US [patent_app_date] => 2014-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 183 [patent_figures_cnt] => 183 [patent_no_of_words] => 67402 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14189387 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/189387
Test circuit adapter circuitry having a link control register Feb 24, 2014 Issued
Array ( [id] => 10651135 [patent_doc_number] => 09367387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-14 [patent_title] => 'Rate adaptive irregular QC-LDPC codes from pairwise balanced designs for ultra-high-speed optical transports' [patent_app_type] => utility [patent_app_number] => 14/162951 [patent_app_country] => US [patent_app_date] => 2014-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5183 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14162951 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/162951
Rate adaptive irregular QC-LDPC codes from pairwise balanced designs for ultra-high-speed optical transports Jan 23, 2014 Issued
Array ( [id] => 11214576 [patent_doc_number] => 09443614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Data pattern generation for I/O testing' [patent_app_type] => utility [patent_app_number] => 14/144417 [patent_app_country] => US [patent_app_date] => 2013-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 10054 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14144417 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/144417
Data pattern generation for I/O testing Dec 29, 2013 Issued
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