Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11078004 [patent_doc_number] => 20160274968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'MEMORY ERASURE INFORMATION IN CACHE LINES' [patent_app_type] => utility [patent_app_number] => 15/034651 [patent_app_country] => US [patent_app_date] => 2013-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8142 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15034651 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/034651
Memory erasure information in cache lines Dec 8, 2013 Issued
Array ( [id] => 9680583 [patent_doc_number] => 08819510 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Selectable JTAG or trace access with data store and output' [patent_app_type] => utility [patent_app_number] => 14/097738 [patent_app_country] => US [patent_app_date] => 2013-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 81 [patent_figures_cnt] => 114 [patent_no_of_words] => 41568 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14097738 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/097738
Selectable JTAG or trace access with data store and output Dec 4, 2013 Issued
Array ( [id] => 10042926 [patent_doc_number] => 09083647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-14 [patent_title] => 'System and method for dynamic signal interference detection during testing of a data packet signal transceiver' [patent_app_type] => utility [patent_app_number] => 14/087584 [patent_app_country] => US [patent_app_date] => 2013-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4260 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14087584 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/087584
System and method for dynamic signal interference detection during testing of a data packet signal transceiver Nov 21, 2013 Issued
Array ( [id] => 11359123 [patent_doc_number] => 09535777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Defect management policies for NAND flash memory' [patent_app_type] => utility [patent_app_number] => 14/087282 [patent_app_country] => US [patent_app_date] => 2013-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8053 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14087282 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/087282
Defect management policies for NAND flash memory Nov 21, 2013 Issued
Array ( [id] => 10264857 [patent_doc_number] => 20150149854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'EARLY DATA TAG TO ALLOW DATA CRC BYPASS VIA A SPECULATIVE MEMORY DATA RETURN PROTOCOL' [patent_app_type] => utility [patent_app_number] => 14/087801 [patent_app_country] => US [patent_app_date] => 2013-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4238 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14087801 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/087801
Early data tag to allow data CRC bypass via a speculative memory data return protocol Nov 21, 2013 Issued
Array ( [id] => 10556214 [patent_doc_number] => 09280415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Semiconductor device, semiconductor system and control method of semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/086565 [patent_app_country] => US [patent_app_date] => 2013-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3012 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14086565 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/086565
Semiconductor device, semiconductor system and control method of semiconductor device Nov 20, 2013 Issued
Array ( [id] => 9540238 [patent_doc_number] => 20140164885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-12 [patent_title] => 'TIME INFORMATION OBTAINING DEVICE AND RADIO-CONTROLLED TIMEPIECE' [patent_app_type] => utility [patent_app_number] => 14/077030 [patent_app_country] => US [patent_app_date] => 2013-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6535 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14077030 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/077030
Time information obtaining device and radio-controlled timepiece Nov 10, 2013 Issued
Array ( [id] => 9800849 [patent_doc_number] => 20150012794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-08 [patent_title] => 'MANAGING NON-VOLATILE MEDIA USING MULTIPLE ERROR CORRECTING CODES' [patent_app_type] => utility [patent_app_number] => 14/076579 [patent_app_country] => US [patent_app_date] => 2013-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 22688 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14076579 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/076579
Managing non-volatile media using multiple error correcting codes Nov 10, 2013 Issued
Array ( [id] => 10250037 [patent_doc_number] => 20150135033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'METHOD AND SYSTEM FOR IMPROVING ERROR CORRECTION IN DATA STORAGE' [patent_app_type] => utility [patent_app_number] => 14/076165 [patent_app_country] => US [patent_app_date] => 2013-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4364 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14076165 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/076165
Method and system for improving error correction in data storage Nov 7, 2013 Issued
Array ( [id] => 10603050 [patent_doc_number] => 09323614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-26 [patent_title] => 'Dynamic error handling for on-chip memory structures' [patent_app_type] => utility [patent_app_number] => 14/073336 [patent_app_country] => US [patent_app_date] => 2013-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8965 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14073336 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/073336
Dynamic error handling for on-chip memory structures Nov 5, 2013 Issued
Array ( [id] => 10243015 [patent_doc_number] => 20150128011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-07 [patent_title] => 'METHODS, CIRCUITS, SYSTEMS AND COMPUTER EXECUTABLE INSTRUCTION SETS FOR PROVIDING ERROR CORRECTION OF STORED DATA AND DATA STORAGE DEVICES UTILIZING SAME' [patent_app_type] => utility [patent_app_number] => 14/073031 [patent_app_country] => US [patent_app_date] => 2013-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4958 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14073031 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/073031
Methods, circuits, systems and computer executable instruction sets for providing error correction of stored data and data storage devices utilizing same Nov 5, 2013 Issued
Array ( [id] => 9431033 [patent_doc_number] => 08707118 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-22 [patent_title] => 'Data, mode and ready bit packets on bidirectional control/data leads' [patent_app_type] => utility [patent_app_number] => 14/053118 [patent_app_country] => US [patent_app_date] => 2013-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 182 [patent_figures_cnt] => 300 [patent_no_of_words] => 67376 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14053118 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/053118
Data, mode and ready bit packets on bidirectional control/data leads Oct 13, 2013 Issued
Array ( [id] => 10215835 [patent_doc_number] => 20150100827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-09 [patent_title] => 'Method of Detecting Bit Errors, An Electronic Circuit for Detecting Bit Errors, and a Data Storage Device' [patent_app_type] => utility [patent_app_number] => 14/045923 [patent_app_country] => US [patent_app_date] => 2013-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3206 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14045923 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/045923
Method of detecting bit errors, an electronic circuit for detecting bit errors, and a data storage device Oct 3, 2013 Issued
Array ( [id] => 9986532 [patent_doc_number] => 09032268 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-05-12 [patent_title] => 'Method for error correction in a multicast network' [patent_app_type] => utility [patent_app_number] => 14/045256 [patent_app_country] => US [patent_app_date] => 2013-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 12721 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14045256 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/045256
Method for error correction in a multicast network Oct 2, 2013 Issued
Array ( [id] => 9933932 [patent_doc_number] => 20150082124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'SPATIALLY DECOUPLED REDUNDANCY SCHEMES FOR A SOLID STATE DRIVE (SSD)' [patent_app_type] => utility [patent_app_number] => 14/045102 [patent_app_country] => US [patent_app_date] => 2013-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4378 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14045102 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/045102
Spatially decoupled redundancy schemes for a solid state drive (SSD) Oct 2, 2013 Issued
Array ( [id] => 10507594 [patent_doc_number] => 09235470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-12 [patent_title] => 'Adaptive EPWR (enhanced post write read) scheduling' [patent_app_type] => utility [patent_app_number] => 14/045294 [patent_app_country] => US [patent_app_date] => 2013-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6365 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14045294 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/045294
Adaptive EPWR (enhanced post write read) scheduling Oct 2, 2013 Issued
Array ( [id] => 9410261 [patent_doc_number] => 20140101513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-10 [patent_title] => 'METHOD OF OPERATING CYCLIC REDUNDANCY CHECK IN MEMORY SYSTEM AND MEMORY CONTROLLER USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/045001 [patent_app_country] => US [patent_app_date] => 2013-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11391 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14045001 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/045001
Method of operating cyclic redundancy check in memory system and memory controller using the same Oct 2, 2013 Issued
Array ( [id] => 10215827 [patent_doc_number] => 20150100819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-09 [patent_title] => 'Method of Recovering Data in a Storage Device' [patent_app_type] => utility [patent_app_number] => 14/045600 [patent_app_country] => US [patent_app_date] => 2013-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6049 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14045600 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/045600
Method of Recovering Data in a Storage Device Oct 2, 2013 Abandoned
Array ( [id] => 9297055 [patent_doc_number] => 20140040689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS' [patent_app_type] => utility [patent_app_number] => 14/044535 [patent_app_country] => US [patent_app_date] => 2013-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5975 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14044535 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/044535
Tap and linking module TDO register, gating for TCK and TMS Oct 1, 2013 Issued
Array ( [id] => 9992713 [patent_doc_number] => 09037935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-19 [patent_title] => 'Apparatus and method for retransmitting message in message transmission system' [patent_app_type] => utility [patent_app_number] => 14/040853 [patent_app_country] => US [patent_app_date] => 2013-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3105 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14040853 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/040853
Apparatus and method for retransmitting message in message transmission system Sep 29, 2013 Issued
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