
Christine Trinh Le Tu
Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784 |
| Total Applications | 1748 |
| Issued Applications | 1571 |
| Pending Applications | 27 |
| Abandoned Applications | 152 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10144857
[patent_doc_number] => 09177670
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-11-03
[patent_title] => 'Method and apparatus for flash cache management'
[patent_app_type] => utility
[patent_app_number] => 14/041290
[patent_app_country] => US
[patent_app_date] => 2013-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 2524
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 42
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14041290
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/041290 | Method and apparatus for flash cache management | Sep 29, 2013 | Issued |
Array
(
[id] => 9933929
[patent_doc_number] => 20150082121
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-03-19
[patent_title] => 'METHOD OF ERASE STATE HANDLING IN FLASH CHANNEL TRACKING'
[patent_app_type] => utility
[patent_app_number] => 14/041110
[patent_app_country] => US
[patent_app_date] => 2013-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4091
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14041110
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/041110 | Method of erase state handling in flash channel tracking | Sep 29, 2013 | Issued |
Array
(
[id] => 9578917
[patent_doc_number] => 08769352
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-07-01
[patent_title] => 'Methods and apparatus for multiple input multiple output (MIMO) successive interference cancellation (SIC) with retransmissions'
[patent_app_type] => utility
[patent_app_number] => 14/016425
[patent_app_country] => US
[patent_app_date] => 2013-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 13164
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14016425
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/016425 | Methods and apparatus for multiple input multiple output (MIMO) successive interference cancellation (SIC) with retransmissions | Sep 2, 2013 | Issued |
Array
(
[id] => 11774503
[patent_doc_number] => 09383408
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-07-05
[patent_title] => 'Fault detection system, generation circuit, and program'
[patent_app_type] => utility
[patent_app_number] => 14/402732
[patent_app_country] => US
[patent_app_date] => 2013-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8230
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14402732
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/402732 | Fault detection system, generation circuit, and program | May 13, 2013 | Issued |
Array
(
[id] => 9555734
[patent_doc_number] => 08762807
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-06-24
[patent_title] => 'Systems and methods for out of order processing in a data retry'
[patent_app_type] => utility
[patent_app_number] => 13/869862
[patent_app_country] => US
[patent_app_date] => 2013-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 6452
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13869862
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/869862 | Systems and methods for out of order processing in a data retry | Apr 23, 2013 | Issued |
Array
(
[id] => 10622732
[patent_doc_number] => 09341672
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-05-17
[patent_title] => 'Method and apparatus for interconnect test'
[patent_app_type] => utility
[patent_app_number] => 13/864492
[patent_app_country] => US
[patent_app_date] => 2013-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 22
[patent_no_of_words] => 6613
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13864492
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/864492 | Method and apparatus for interconnect test | Apr 16, 2013 | Issued |
Array
(
[id] => 11509205
[patent_doc_number] => 09600365
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-03-21
[patent_title] => 'Local erasure codes for data storage'
[patent_app_type] => utility
[patent_app_number] => 13/863912
[patent_app_country] => US
[patent_app_date] => 2013-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7145
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 385
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13863912
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/863912 | Local erasure codes for data storage | Apr 15, 2013 | Issued |
Array
(
[id] => 9017420
[patent_doc_number] => 20130232384
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-05
[patent_title] => 'METHOD AND SYSTEM FOR ITERATIVELY TESTING AND REPAIRING AN ARRAY OF MEMORY CELLS'
[patent_app_type] => utility
[patent_app_number] => 13/862738
[patent_app_country] => US
[patent_app_date] => 2013-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 11186
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13862738
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/862738 | Method and system for iteratively testing and repairing an array of memory cells | Apr 14, 2013 | Issued |
Array
(
[id] => 9017424
[patent_doc_number] => 20130232387
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-05
[patent_title] => 'SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT'
[patent_app_type] => utility
[patent_app_number] => 13/851587
[patent_app_country] => US
[patent_app_date] => 2013-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 82
[patent_figures_cnt] => 82
[patent_no_of_words] => 41388
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13851587
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/851587 | Trace circuitry connected to TAP domain and address-command port | Mar 26, 2013 | Issued |
Array
(
[id] => 9961351
[patent_doc_number] => 09009576
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-04-14
[patent_title] => 'Adaptive LLR based on syndrome weight'
[patent_app_type] => utility
[patent_app_number] => 13/831713
[patent_app_country] => US
[patent_app_date] => 2013-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 13640
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13831713
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/831713 | Adaptive LLR based on syndrome weight | Mar 14, 2013 | Issued |
Array
(
[id] => 9746113
[patent_doc_number] => 20140281832
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-18
[patent_title] => 'SYSTEM AND METHOD FOR CYCLE SLIP CORRECTION'
[patent_app_type] => utility
[patent_app_number] => 13/833667
[patent_app_country] => US
[patent_app_date] => 2013-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6613
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13833667
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/833667 | System and method for cycle slip correction | Mar 14, 2013 | Issued |
Array
(
[id] => 9746125
[patent_doc_number] => 20140281844
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-18
[patent_title] => 'MODULAR AND SCALABLE CYCLIC REDUNDANCY CHECK COMPUTATION CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 13/841574
[patent_app_country] => US
[patent_app_date] => 2013-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 9921
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13841574
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/841574 | Modular and scalable cyclic redundancy check computation circuit | Mar 14, 2013 | Issued |
Array
(
[id] => 11179686
[patent_doc_number] => 09411679
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-08-09
[patent_title] => 'Code modulation encoder and decoder, memory controller including them, and flash memory system'
[patent_app_type] => utility
[patent_app_number] => 13/834010
[patent_app_country] => US
[patent_app_date] => 2013-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 27
[patent_no_of_words] => 13047
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13834010
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/834010 | Code modulation encoder and decoder, memory controller including them, and flash memory system | Mar 14, 2013 | Issued |
Array
(
[id] => 10292322
[patent_doc_number] => 20150177321
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-25
[patent_title] => 'DEVICE FOR TESTING AND MONITORING DIGITAL CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 14/403127
[patent_app_country] => US
[patent_app_date] => 2013-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6195
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14403127
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/403127 | DEVICE FOR TESTING AND MONITORING DIGITAL CIRCUITS | Mar 14, 2013 | Abandoned |
Array
(
[id] => 10543551
[patent_doc_number] => 09268683
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-02-23
[patent_title] => 'Storage method and apparatus for random access memory using codeword storage'
[patent_app_type] => utility
[patent_app_number] => 13/844032
[patent_app_country] => US
[patent_app_date] => 2013-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6444
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13844032
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/844032 | Storage method and apparatus for random access memory using codeword storage | Mar 14, 2013 | Issued |
Array
(
[id] => 11584774
[patent_doc_number] => 09639416
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-05-02
[patent_title] => 'CRC circuits with extended cycles'
[patent_app_type] => utility
[patent_app_number] => 13/831466
[patent_app_country] => US
[patent_app_date] => 2013-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 29
[patent_no_of_words] => 18783
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13831466
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/831466 | CRC circuits with extended cycles | Mar 13, 2013 | Issued |
Array
(
[id] => 9746112
[patent_doc_number] => 20140281831
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-18
[patent_title] => 'PACKET LOSS RECOVERY'
[patent_app_type] => utility
[patent_app_number] => 13/795842
[patent_app_country] => US
[patent_app_date] => 2013-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6235
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13795842
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/795842 | Packet loss recovery | Mar 11, 2013 | Issued |
Array
(
[id] => 9071192
[patent_doc_number] => 20130262948
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-03
[patent_title] => 'RECEPTION CIRCUIT, INFORMATION PROCESSING APPARATUS, AND CONTROL METHOD'
[patent_app_type] => utility
[patent_app_number] => 13/793754
[patent_app_country] => US
[patent_app_date] => 2013-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6750
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13793754
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/793754 | Reception circuit, information processing apparatus, and control method | Mar 10, 2013 | Issued |
Array
(
[id] => 9723097
[patent_doc_number] => 20140258798
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-11
[patent_title] => 'TEST CONTROL POINT INSERTION AND X-BOUNDING FOR LOGIC BUILT-IN SELF-TEST (LBIST) USING OBSERVATION CIRCUITRY'
[patent_app_type] => utility
[patent_app_number] => 13/788344
[patent_app_country] => US
[patent_app_date] => 2013-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4603
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13788344
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/788344 | Test control point insertion and X-bounding for logic built-in self-test (LBIST) using observation circuitry | Mar 6, 2013 | Issued |
Array
(
[id] => 9365379
[patent_doc_number] => 20140075252
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-03-13
[patent_title] => 'Erased Page Confirmation in Multilevel Memory'
[patent_app_type] => utility
[patent_app_number] => 13/784693
[patent_app_country] => US
[patent_app_date] => 2013-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7394
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13784693
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/784693 | Erased page confirmation in multilevel memory | Mar 3, 2013 | Issued |