Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10633948 [patent_doc_number] => RE046021 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2016-05-31 [patent_title] => 'System-on-chip with master/slave debug interface' [patent_app_type] => reissue [patent_app_number] => 13/775962 [patent_app_country] => US [patent_app_date] => 2013-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2008 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13775962 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/775962
System-on-chip with master/slave debug interface Feb 24, 2013 Issued
Array ( [id] => 9707444 [patent_doc_number] => 08832539 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-09-09 [patent_title] => 'Write processing for unchanged data with new metadata' [patent_app_type] => utility [patent_app_number] => 13/739370 [patent_app_country] => US [patent_app_date] => 2013-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3553 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13739370 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/739370
Write processing for unchanged data with new metadata Jan 10, 2013 Issued
Array ( [id] => 9714479 [patent_doc_number] => 08839082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Methods for viterbi decoder implementation' [patent_app_type] => utility [patent_app_number] => 13/739852 [patent_app_country] => US [patent_app_date] => 2013-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6128 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13739852 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/739852
Methods for viterbi decoder implementation Jan 10, 2013 Issued
Array ( [id] => 9283028 [patent_doc_number] => 20140032996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'DECODING APPARATUS, STORAGE APPARATUS, AND DECODING METHOD' [patent_app_type] => utility [patent_app_number] => 13/738749 [patent_app_country] => US [patent_app_date] => 2013-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5421 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13738749 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/738749
Decoding apparatus, storage apparatus, and decoding method Jan 9, 2013 Issued
Array ( [id] => 9130268 [patent_doc_number] => 08578225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-05 [patent_title] => 'One agumentation instruction register coupled to plural TAP instruction registers' [patent_app_type] => utility [patent_app_number] => 13/737474 [patent_app_country] => US [patent_app_date] => 2013-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5960 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13737474 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/737474
One agumentation instruction register coupled to plural TAP instruction registers Jan 8, 2013 Issued
Array ( [id] => 9599172 [patent_doc_number] => 20140195852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'MEMORY TESTING OF THREE DIMENSIONAL (3D) STACKED MEMORY' [patent_app_type] => utility [patent_app_number] => 13/737063 [patent_app_country] => US [patent_app_date] => 2013-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12012 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13737063 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/737063
Memory testing of three dimensional (3D) stacked memory Jan 8, 2013 Issued
Array ( [id] => 9044230 [patent_doc_number] => 20130246868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/736238 [patent_app_country] => US [patent_app_date] => 2013-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6289 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13736238 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/736238
Arithmetic processing apparatus and method of controlling arithmetic processing apparatus Jan 7, 2013 Issued
Array ( [id] => 8918130 [patent_doc_number] => 20130179755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-11 [patent_title] => 'SYSTEMS AND METHODS FOR LOW DENSITY PARITY CHECK TONE MAPPING' [patent_app_type] => utility [patent_app_number] => 13/735747 [patent_app_country] => US [patent_app_date] => 2013-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10477 [patent_no_of_claims] => 88 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13735747 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/735747
SYSTEMS AND METHODS FOR LOW DENSITY PARITY CHECK TONE MAPPING Jan 6, 2013 Abandoned
Array ( [id] => 9365382 [patent_doc_number] => 20140075255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'DEBUGGING CONTROL SYSTEM USING INSIDE CORE EVENT AS TRIGGER CONDITION AND METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 13/735082 [patent_app_country] => US [patent_app_date] => 2013-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5416 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13735082 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/735082
Debugging control system using inside core event as trigger condition and method of the same Jan 6, 2013 Issued
Array ( [id] => 9571743 [patent_doc_number] => 20140189455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'SYSTEM FOR REDUCING PEAK POWER DURING SCAN SHIFT AT THE GLOBAL LEVEL FOR SCAN BASED TESTS' [patent_app_type] => utility [patent_app_number] => 13/730628 [patent_app_country] => US [patent_app_date] => 2012-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9741 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730628 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/730628
System for reducing peak power during scan shift at the global level for scan based tests Dec 27, 2012 Issued
Array ( [id] => 9912252 [patent_doc_number] => 20150067454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'METHOD OF TRANSMITTING A DIGITAL SIGNAL FOR A SEMI-ORTHOGONAL MS-MARC SYSTEM, AND A CORRESPONDING PROGRAM PRODUCT AND RELAY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/367719 [patent_app_country] => US [patent_app_date] => 2012-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11755 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14367719 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/367719
Method of transmitting a digital signal for a semi-orthogonal MS-marc system, and a corresponding program product and relay device Dec 19, 2012 Issued
Array ( [id] => 10104964 [patent_doc_number] => 09140741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-22 [patent_title] => 'Integrated circuit chip and memory device having the same' [patent_app_type] => utility [patent_app_number] => 13/720191 [patent_app_country] => US [patent_app_date] => 2012-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4070 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13720191 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/720191
Integrated circuit chip and memory device having the same Dec 18, 2012 Issued
Array ( [id] => 8918119 [patent_doc_number] => 20130179743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-11 [patent_title] => 'SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS' [patent_app_type] => utility [patent_app_number] => 13/693535 [patent_app_country] => US [patent_app_date] => 2012-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 183 [patent_figures_cnt] => 183 [patent_no_of_words] => 67425 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13693535 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/693535
Bidirectional clock, data, and control to functional and test circuitry Dec 3, 2012 Issued
Array ( [id] => 15757853 [patent_doc_number] => 10621040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Memory controllers to form symbols based on bursts [patent_app_type] => utility [patent_app_number] => 14/648290 [patent_app_country] => US [patent_app_date] => 2012-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3079 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14648290 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/648290
Memory controllers to form symbols based on bursts Nov 29, 2012 Issued
Array ( [id] => 10885623 [patent_doc_number] => 08910026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-09 [patent_title] => 'Data decoding using side information' [patent_app_type] => utility [patent_app_number] => 13/675172 [patent_app_country] => US [patent_app_date] => 2012-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9556 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13675172 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/675172
Data decoding using side information Nov 12, 2012 Issued
Array ( [id] => 9886037 [patent_doc_number] => 08972822 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Memory module and semiconductor storage device' [patent_app_type] => utility [patent_app_number] => 13/675265 [patent_app_country] => US [patent_app_date] => 2012-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4311 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13675265 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/675265
Memory module and semiconductor storage device Nov 12, 2012 Issued
Array ( [id] => 9947635 [patent_doc_number] => 08996963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-31 [patent_title] => 'Buffer management using side information' [patent_app_type] => utility [patent_app_number] => 13/675177 [patent_app_country] => US [patent_app_date] => 2012-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9553 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13675177 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/675177
Buffer management using side information Nov 12, 2012 Issued
Array ( [id] => 8823893 [patent_doc_number] => 20130124938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING A QUASI-CYCLIC LOW DENSITY PARITY CHECK CODE IN A MULTIMEDIA COMMUNICATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/674651 [patent_app_country] => US [patent_app_date] => 2012-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 32653 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13674651 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/674651
Apparatus and method for transmitting and receiving a quasi-cyclic low density parity check code in a multimedia communication system Nov 11, 2012 Issued
Array ( [id] => 8787108 [patent_doc_number] => 08433963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-30 [patent_title] => 'Address and command port connecting trace circuitry and TAP domain' [patent_app_type] => utility [patent_app_number] => 13/627553 [patent_app_country] => US [patent_app_date] => 2012-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 81 [patent_figures_cnt] => 114 [patent_no_of_words] => 41507 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13627553 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/627553
Address and command port connecting trace circuitry and TAP domain Sep 25, 2012 Issued
Array ( [id] => 8709292 [patent_doc_number] => 20130066581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-14 [patent_title] => 'INTEGRATED CIRCUIT TESTING MODULE INCLUDING SIGNAL SHAPING INTERFACE' [patent_app_type] => utility [patent_app_number] => 13/609019 [patent_app_country] => US [patent_app_date] => 2012-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 21974 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13609019 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/609019
Integrated circuit testing module including signal shaping interface Sep 9, 2012 Issued
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