Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11411474 [patent_doc_number] => 09558782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'Partial reverse concatenation for data storage devices using composite codes' [patent_app_type] => utility [patent_app_number] => 13/483015 [patent_app_country] => US [patent_app_date] => 2012-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 10255 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13483015 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/483015
Partial reverse concatenation for data storage devices using composite codes May 28, 2012 Issued
Array ( [id] => 9652258 [patent_doc_number] => 08806295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'Mis-correction and no-correction rates for error control' [patent_app_type] => utility [patent_app_number] => 13/479855 [patent_app_country] => US [patent_app_date] => 2012-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7240 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13479855 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/479855
Mis-correction and no-correction rates for error control May 23, 2012 Issued
Array ( [id] => 9623362 [patent_doc_number] => 08793556 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-07-29 [patent_title] => 'Systems and methods for reclaiming flash blocks of a flash drive' [patent_app_type] => utility [patent_app_number] => 13/477845 [patent_app_country] => US [patent_app_date] => 2012-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 37117 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13477845 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/477845
Systems and methods for reclaiming flash blocks of a flash drive May 21, 2012 Issued
Array ( [id] => 9062914 [patent_doc_number] => 08549368 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-01 [patent_title] => 'Memory built-in-self testing in multi-core integrated circuit' [patent_app_type] => utility [patent_app_number] => 13/475948 [patent_app_country] => US [patent_app_date] => 2012-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4741 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13475948 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/475948
Memory built-in-self testing in multi-core integrated circuit May 18, 2012 Issued
Array ( [id] => 9986524 [patent_doc_number] => 09032260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-12 [patent_title] => 'Parallel bit interleaver' [patent_app_type] => utility [patent_app_number] => 14/116608 [patent_app_country] => US [patent_app_date] => 2012-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 35 [patent_no_of_words] => 11571 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14116608 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/116608
Parallel bit interleaver May 17, 2012 Issued
Array ( [id] => 8497868 [patent_doc_number] => 20120297276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-22 [patent_title] => 'TECHNIQUES FOR RATE MATCHING AND DE-RATE MATCHING' [patent_app_type] => utility [patent_app_number] => 13/475940 [patent_app_country] => US [patent_app_date] => 2012-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4348 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13475940 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/475940
Techniques for rate matching and de-rate matching May 17, 2012 Issued
Array ( [id] => 9999053 [patent_doc_number] => 09043669 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-05-26 [patent_title] => 'Distributed ECC engine for storage media' [patent_app_type] => utility [patent_app_number] => 13/475878 [patent_app_country] => US [patent_app_date] => 2012-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17198 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13475878 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/475878
Distributed ECC engine for storage media May 17, 2012 Issued
Array ( [id] => 9465468 [patent_doc_number] => 20140129895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'PARALLEL BIT INTERLEAVER' [patent_app_type] => utility [patent_app_number] => 14/116632 [patent_app_country] => US [patent_app_date] => 2012-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 57 [patent_no_of_words] => 20530 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14116632 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/116632
PARALLEL BIT INTERLEAVER May 17, 2012 Abandoned
Array ( [id] => 9163569 [patent_doc_number] => 20130311846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-21 [patent_title] => 'Systems and Methods for Hardware Flexible Low Density Parity Check Conversion' [patent_app_type] => utility [patent_app_number] => 13/474664 [patent_app_country] => US [patent_app_date] => 2012-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6237 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13474664 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/474664
Systems and methods for hardware flexible low density parity check conversion May 16, 2012 Issued
Array ( [id] => 9163568 [patent_doc_number] => 20130311845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-21 [patent_title] => 'SYSTEMS AND METHODS FOR NON-BINARY LDPC ENCODING' [patent_app_type] => utility [patent_app_number] => 13/474660 [patent_app_country] => US [patent_app_date] => 2012-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5538 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13474660 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/474660
Systems and methods for non-binary LDPC encoding May 16, 2012 Issued
Array ( [id] => 9926389 [patent_doc_number] => 08984374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-17 [patent_title] => 'Storage system and storage control apparatus' [patent_app_type] => utility [patent_app_number] => 13/510299 [patent_app_country] => US [patent_app_date] => 2012-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 92 [patent_figures_cnt] => 92 [patent_no_of_words] => 34601 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13510299 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/510299
Storage system and storage control apparatus Apr 26, 2012 Issued
Array ( [id] => 9156854 [patent_doc_number] => 08589768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Memory system having multiple channels and write control method including determination of error correction channel in memory system' [patent_app_type] => utility [patent_app_number] => 13/421538 [patent_app_country] => US [patent_app_date] => 2012-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4436 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13421538 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/421538
Memory system having multiple channels and write control method including determination of error correction channel in memory system Mar 14, 2012 Issued
Array ( [id] => 9044237 [patent_doc_number] => 20130246875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'Multi-Modal Signal Processing with Linearization' [patent_app_type] => utility [patent_app_number] => 13/421328 [patent_app_country] => US [patent_app_date] => 2012-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11295 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13421328 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/421328
Multi-modal signal processing with linearization Mar 14, 2012 Issued
Array ( [id] => 10644309 [patent_doc_number] => 09361181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'Error protection for memory devices' [patent_app_type] => utility [patent_app_number] => 13/421578 [patent_app_country] => US [patent_app_date] => 2012-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 8099 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13421578 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/421578
Error protection for memory devices Mar 14, 2012 Issued
Array ( [id] => 9940832 [patent_doc_number] => 08990665 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-03-24 [patent_title] => 'System, method and computer program product for joint search of a read threshold and soft decoding' [patent_app_type] => utility [patent_app_number] => 13/420032 [patent_app_country] => US [patent_app_date] => 2012-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12543 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13420032 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/420032
System, method and computer program product for joint search of a read threshold and soft decoding Mar 13, 2012 Issued
Array ( [id] => 8929848 [patent_doc_number] => 20130185608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-18 [patent_title] => 'SCAN CHAIN ACCESS IN 3D STACKED INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 13/420099 [patent_app_country] => US [patent_app_date] => 2012-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13420099 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/420099
SCAN CHAIN ACCESS IN 3D STACKED INTEGRATED CIRCUITS Mar 13, 2012 Abandoned
Array ( [id] => 9714473 [patent_doc_number] => 08839076 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Encoding a data word for writing the encoded data word in a multi-level solid state memory' [patent_app_type] => utility [patent_app_number] => 13/418423 [patent_app_country] => US [patent_app_date] => 2012-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9322 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13418423 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/418423
Encoding a data word for writing the encoded data word in a multi-level solid state memory Mar 12, 2012 Issued
Array ( [id] => 8395672 [patent_doc_number] => 20120233512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'Two-Dimensional Scan Architecture' [patent_app_type] => utility [patent_app_number] => 13/416912 [patent_app_country] => US [patent_app_date] => 2012-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3420 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13416912 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/416912
Two-dimensional scan architecture Mar 8, 2012 Issued
Array ( [id] => 9714481 [patent_doc_number] => 08839084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Digital architectures for serial data stream operations' [patent_app_type] => utility [patent_app_number] => 13/416994 [patent_app_country] => US [patent_app_date] => 2012-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4722 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13416994 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/416994
Digital architectures for serial data stream operations Mar 8, 2012 Issued
Array ( [id] => 8455097 [patent_doc_number] => 20120266043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/416144 [patent_app_country] => US [patent_app_date] => 2012-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9727 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13416144 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/416144
Semiconductor memory device Mar 8, 2012 Issued
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