
Christine Trinh Le Tu
Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784 |
| Total Applications | 1748 |
| Issued Applications | 1571 |
| Pending Applications | 27 |
| Abandoned Applications | 152 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10515823
[patent_doc_number] => 09242858
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-01-26
[patent_title] => 'Instruction register delay select outputs to clock delay circuitry'
[patent_app_type] => utility
[patent_app_number] => 13/097362
[patent_app_country] => US
[patent_app_date] => 2011-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 42
[patent_no_of_words] => 13646
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13097362
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/097362 | Instruction register delay select outputs to clock delay circuitry | Apr 28, 2011 | Issued |
Array
(
[id] => 6166738
[patent_doc_number] => 20110161757
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-06-30
[patent_title] => 'TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS'
[patent_app_type] => utility
[patent_app_number] => 13/043763
[patent_app_country] => US
[patent_app_date] => 2011-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5884
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0161/20110161757.pdf
[firstpage_image] =>[orig_patent_app_number] => 13043763
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/043763 | TAP linking module TDI multiplexer circuitry to plural TAPs | Mar 8, 2011 | Issued |
Array
(
[id] => 10860813
[patent_doc_number] => 08887030
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-11-11
[patent_title] => 'Encoder and encoding method providing incremental redundancy'
[patent_app_type] => utility
[patent_app_number] => 13/579735
[patent_app_country] => US
[patent_app_date] => 2011-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 43
[patent_figures_cnt] => 60
[patent_no_of_words] => 20417
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13579735
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/579735 | Encoder and encoding method providing incremental redundancy | Feb 17, 2011 | Issued |
Array
(
[id] => 6006212
[patent_doc_number] => 20110119541
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-05-19
[patent_title] => 'BDX DATA IN STABLE STATES'
[patent_app_type] => utility
[patent_app_number] => 13/014486
[patent_app_country] => US
[patent_app_date] => 2011-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 11979
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0119/20110119541.pdf
[firstpage_image] =>[orig_patent_app_number] => 13014486
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/014486 | BDX DATA IN STABLE STATES | Jan 25, 2011 | Abandoned |
Array
(
[id] => 6131413
[patent_doc_number] => 20110087936
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-04-14
[patent_title] => 'SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT'
[patent_app_type] => utility
[patent_app_number] => 12/970148
[patent_app_country] => US
[patent_app_date] => 2010-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 82
[patent_figures_cnt] => 82
[patent_no_of_words] => 41389
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0087/20110087936.pdf
[firstpage_image] =>[orig_patent_app_number] => 12970148
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/970148 | Communication between controller and addressed target devices over data signal | Dec 15, 2010 | Issued |
Array
(
[id] => 6073812
[patent_doc_number] => 20110047420
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-02-24
[patent_title] => 'METHOD AND SYSTEM FOR TESTING CHIPS'
[patent_app_type] => utility
[patent_app_number] => 12/938392
[patent_app_country] => US
[patent_app_date] => 2010-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1724
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0047/20110047420.pdf
[firstpage_image] =>[orig_patent_app_number] => 12938392
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/938392 | Method and system for testing chips | Nov 2, 2010 | Issued |
Array
(
[id] => 8319737
[patent_doc_number] => 08234531
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-07-31
[patent_title] => 'System-on-chip with master/slave debug interface'
[patent_app_type] => utility
[patent_app_number] => 12/913236
[patent_app_country] => US
[patent_app_date] => 2010-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1908
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12913236
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/913236 | System-on-chip with master/slave debug interface | Oct 26, 2010 | Issued |
Array
(
[id] => 8485177
[patent_doc_number] => 20120284584
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-08
[patent_title] => 'DECODING METHOD AND DEVICE FOR CONCATENATED CODE'
[patent_app_type] => utility
[patent_app_number] => 13/512196
[patent_app_country] => US
[patent_app_date] => 2010-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4533
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13512196
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/512196 | Decoding method and device for concatenated code | Oct 21, 2010 | Issued |
Array
(
[id] => 6363675
[patent_doc_number] => 20100332926
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-12-30
[patent_title] => 'APPARATUS FOR FORMATTING INFORMATION STORAGE MEDIUM'
[patent_app_type] => utility
[patent_app_number] => 12/879048
[patent_app_country] => US
[patent_app_date] => 2010-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 14090
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0332/20100332926.pdf
[firstpage_image] =>[orig_patent_app_number] => 12879048
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/879048 | Apparatus for formatting information storage medium | Sep 9, 2010 | Issued |
Array
(
[id] => 4559644
[patent_doc_number] => 07877654
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-01-25
[patent_title] => 'Selectable JTAG or trace access with data store and output'
[patent_app_type] => utility
[patent_app_number] => 12/822694
[patent_app_country] => US
[patent_app_date] => 2010-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 81
[patent_figures_cnt] => 114
[patent_no_of_words] => 41354
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/877/07877654.pdf
[firstpage_image] =>[orig_patent_app_number] => 12822694
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/822694 | Selectable JTAG or trace access with data store and output | Jun 23, 2010 | Issued |
Array
(
[id] => 4443561
[patent_doc_number] => 07900109
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-03-01
[patent_title] => 'BDX data in stable states'
[patent_app_type] => utility
[patent_app_number] => 12/814990
[patent_app_country] => US
[patent_app_date] => 2010-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 42
[patent_no_of_words] => 11952
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/900/07900109.pdf
[firstpage_image] =>[orig_patent_app_number] => 12814990
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/814990 | BDX data in stable states | Jun 13, 2010 | Issued |
Array
(
[id] => 6270730
[patent_doc_number] => 20100299096
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-11-25
[patent_title] => 'DELAY FAULT TESTING COMPUTER PRODUCT, APPARATUS, AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 12/778329
[patent_app_country] => US
[patent_app_date] => 2010-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 10875
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0299/20100299096.pdf
[firstpage_image] =>[orig_patent_app_number] => 12778329
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/778329 | Delay fault testing computer product, apparatus, and method | May 11, 2010 | Issued |
Array
(
[id] => 6565198
[patent_doc_number] => 20100223519
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-09-02
[patent_title] => 'COMPACT JTAG ADAPTER'
[patent_app_type] => utility
[patent_app_number] => 12/776579
[patent_app_country] => US
[patent_app_date] => 2010-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 183
[patent_figures_cnt] => 183
[patent_no_of_words] => 67506
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 17
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0223/20100223519.pdf
[firstpage_image] =>[orig_patent_app_number] => 12776579
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/776579 | JTAG debug test system adapter with three sets of leads | May 9, 2010 | Issued |
Array
(
[id] => 9289429
[patent_doc_number] => 08645787
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-02-04
[patent_title] => 'Method for controlling a basic parity node of a non-binary LDPC code decoder, and corresponding basic parity node processor'
[patent_app_type] => utility
[patent_app_number] => 13/319033
[patent_app_country] => US
[patent_app_date] => 2010-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 8449
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 516
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13319033
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/319033 | Method for controlling a basic parity node of a non-binary LDPC code decoder, and corresponding basic parity node processor | May 4, 2010 | Issued |
Array
(
[id] => 6253223
[patent_doc_number] => 20100138695
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-06-03
[patent_title] => 'Signal Integrity Measurement Systems and Methods Using a Predominantly Digital Time-Base Generator'
[patent_app_type] => utility
[patent_app_number] => 12/701282
[patent_app_country] => US
[patent_app_date] => 2010-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 10424
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0138/20100138695.pdf
[firstpage_image] =>[orig_patent_app_number] => 12701282
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/701282 | Signal Integrity Measurement Systems and Methods Using a Predominantly Digital Time-Base Generator | Feb 4, 2010 | Abandoned |
Array
(
[id] => 6629367
[patent_doc_number] => 20100100780
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-22
[patent_title] => 'HIGH SPEED INTERCONNECT CIRCUIT TEST METHOD AND APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 12/640896
[patent_app_country] => US
[patent_app_date] => 2009-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 13641
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0100/20100100780.pdf
[firstpage_image] =>[orig_patent_app_number] => 12640896
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/640896 | Clock delay circuits and multiplexer connected to boundary scan circuitry | Dec 16, 2009 | Issued |
Array
(
[id] => 6388635
[patent_doc_number] => 20100083065
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-01
[patent_title] => 'Method and apparatus for error detection and correction'
[patent_app_type] => utility
[patent_app_number] => 12/592645
[patent_app_country] => US
[patent_app_date] => 2009-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8920
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0083/20100083065.pdf
[firstpage_image] =>[orig_patent_app_number] => 12592645
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/592645 | Method and apparatus for error detection and correction | Nov 30, 2009 | Abandoned |
Array
(
[id] => 8878806
[patent_doc_number] => 08473790
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-06-25
[patent_title] => 'Method for correcting prediction errors of signal values with time variation subjected to interference by various uncontrollable systematic effects'
[patent_app_type] => utility
[patent_app_number] => 13/126280
[patent_app_country] => US
[patent_app_date] => 2009-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2830
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13126280
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/126280 | Method for correcting prediction errors of signal values with time variation subjected to interference by various uncontrollable systematic effects | Oct 26, 2009 | Issued |
Array
(
[id] => 5372870
[patent_doc_number] => 20090310430
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-17
[patent_title] => 'METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRONIC MEMORY CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 12/542187
[patent_app_country] => US
[patent_app_date] => 2009-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 8112
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0310/20090310430.pdf
[firstpage_image] =>[orig_patent_app_number] => 12542187
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/542187 | Methods for characterizing device variation in electronic memory circuits | Aug 16, 2009 | Issued |
Array
(
[id] => 4550098
[patent_doc_number] => 07925942
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-04-12
[patent_title] => 'Augmentation instruction shift register with serial and two parallel inputs'
[patent_app_type] => utility
[patent_app_number] => 12/539373
[patent_app_country] => US
[patent_app_date] => 2009-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 5867
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 247
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/925/07925942.pdf
[firstpage_image] =>[orig_patent_app_number] => 12539373
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/539373 | Augmentation instruction shift register with serial and two parallel inputs | Aug 10, 2009 | Issued |