Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7575511 [patent_doc_number] => 20110271167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'Parallel Associative Memory' [patent_app_type] => utility [patent_app_number] => 13/123902 [patent_app_country] => US [patent_app_date] => 2009-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6374 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20110271167.pdf [firstpage_image] =>[orig_patent_app_number] => 13123902 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/123902
Parallel Associative Memory Aug 3, 2009 Abandoned
Array ( [id] => 4573420 [patent_doc_number] => 07962814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Mode selection based on special sequence of state machine states' [patent_app_type] => utility [patent_app_number] => 12/496267 [patent_app_country] => US [patent_app_date] => 2009-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 42 [patent_no_of_words] => 11999 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/962/07962814.pdf [firstpage_image] =>[orig_patent_app_number] => 12496267 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/496267
Mode selection based on special sequence of state machine states Jun 30, 2009 Issued
Array ( [id] => 58755 [patent_doc_number] => 07770084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'Selectable JTAG or trace access with data store and output' [patent_app_type] => utility [patent_app_number] => 12/493881 [patent_app_country] => US [patent_app_date] => 2009-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 81 [patent_figures_cnt] => 114 [patent_no_of_words] => 41228 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/770/07770084.pdf [firstpage_image] =>[orig_patent_app_number] => 12493881 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/493881
Selectable JTAG or trace access with data store and output Jun 28, 2009 Issued
Array ( [id] => 5486899 [patent_doc_number] => 20090276664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-05 [patent_title] => 'METHOD AND APPARATUS FOR MONITORING BIT-ERROR RATE' [patent_app_type] => utility [patent_app_number] => 12/480629 [patent_app_country] => US [patent_app_date] => 2009-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3938 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20090276664.pdf [firstpage_image] =>[orig_patent_app_number] => 12480629 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/480629
Method and apparatus for monitoring bit-error rate Jun 7, 2009 Issued
Array ( [id] => 7591354 [patent_doc_number] => 07653853 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-01-26 [patent_title] => 'Integrated circuit internal test circuit and method of testing by using test pattern and signature generations therewith' [patent_app_type] => utility [patent_app_number] => 12/416336 [patent_app_country] => US [patent_app_date] => 2009-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6194 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/653/07653853.pdf [firstpage_image] =>[orig_patent_app_number] => 12416336 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/416336
Integrated circuit internal test circuit and method of testing by using test pattern and signature generations therewith Mar 31, 2009 Issued
Array ( [id] => 4443543 [patent_doc_number] => 07900104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Test pattern compression for an integrated circuit test environment' [patent_app_type] => utility [patent_app_number] => 12/405409 [patent_app_country] => US [patent_app_date] => 2009-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8091 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/900/07900104.pdf [firstpage_image] =>[orig_patent_app_number] => 12405409 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/405409
Test pattern compression for an integrated circuit test environment Mar 16, 2009 Issued
Array ( [id] => 7686355 [patent_doc_number] => 20090177936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'DIRECT LOGIC DIAGNOSTICS WITH SIGNATURE-BASED FAULT DICTIONARIES' [patent_app_type] => utility [patent_app_number] => 12/404553 [patent_app_country] => US [patent_app_date] => 2009-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11295 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20090177936.pdf [firstpage_image] =>[orig_patent_app_number] => 12404553 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/404553
Direct logic diagnostics with signature-based fault dictionaries Mar 15, 2009 Issued
Array ( [id] => 5548226 [patent_doc_number] => 20090158103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'TEST APPARATUS AND TEST METHOD' [patent_app_type] => utility [patent_app_number] => 12/388802 [patent_app_country] => US [patent_app_date] => 2009-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6510 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158103.pdf [firstpage_image] =>[orig_patent_app_number] => 12388802 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/388802
Test apparatus and test method with features of adjusting phase difference between data and reference clock and acquiring adjusted data Feb 18, 2009 Issued
Array ( [id] => 5280742 [patent_doc_number] => 20090132874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'SYSTEM AND METHOD FOR TESTING A DATA STORAGE DEVICE WITHOUT REVEALING MEMORY CONTENT' [patent_app_type] => utility [patent_app_number] => 12/356368 [patent_app_country] => US [patent_app_date] => 2009-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 3433 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20090132874.pdf [firstpage_image] =>[orig_patent_app_number] => 12356368 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/356368
System and method for testing a data storage device without revealing memory content Jan 19, 2009 Issued
Array ( [id] => 5280750 [patent_doc_number] => 20090132882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'Scan-load-based dynamic scan configuration' [patent_app_type] => utility [patent_app_number] => 12/321170 [patent_app_country] => US [patent_app_date] => 2009-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7627 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20090132882.pdf [firstpage_image] =>[orig_patent_app_number] => 12321170 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/321170
Scan-load-based dynamic scan configuration Jan 15, 2009 Issued
Array ( [id] => 5266872 [patent_doc_number] => 20090119557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'HIGH SPEED INTERCONNECT CIRCUIT TEST METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/351462 [patent_app_country] => US [patent_app_date] => 2009-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13614 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20090119557.pdf [firstpage_image] =>[orig_patent_app_number] => 12351462 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/351462
Propagation test strobe circuitry with boundary scan circuitry Jan 8, 2009 Issued
Array ( [id] => 5266870 [patent_doc_number] => 20090119555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'Hyperjtag System Including Debug Probe, On-Chip Instrumentation, and Protocol' [patent_app_type] => utility [patent_app_number] => 12/348847 [patent_app_country] => US [patent_app_date] => 2009-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8395 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20090119555.pdf [firstpage_image] =>[orig_patent_app_number] => 12348847 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/348847
Hyperjtag system including debug probe, on-chip instrumentation, and protocol Jan 4, 2009 Issued
Array ( [id] => 6020568 [patent_doc_number] => 20110225478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'COMMUNICATION APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/130535 [patent_app_country] => US [patent_app_date] => 2008-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9048 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20110225478.pdf [firstpage_image] =>[orig_patent_app_number] => 13130535 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/130535
Communication apparatus Nov 26, 2008 Issued
Array ( [id] => 5266878 [patent_doc_number] => 20090119563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'METHOD AND APPARATUS FOR TESTING LOGIC CIRCUIT DESIGNS' [patent_app_type] => utility [patent_app_number] => 12/265300 [patent_app_country] => US [patent_app_date] => 2008-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10851 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20090119563.pdf [firstpage_image] =>[orig_patent_app_number] => 12265300 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/265300
Method for generating, from a test cube set, a generator configured to generate a test pattern Nov 4, 2008 Issued
Array ( [id] => 5266871 [patent_doc_number] => 20090119556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'METHOD AND APPARATUS FOR TESTING LOGIC CIRCUIT DESIGNS' [patent_app_type] => utility [patent_app_number] => 12/265330 [patent_app_country] => US [patent_app_date] => 2008-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10850 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20090119556.pdf [firstpage_image] =>[orig_patent_app_number] => 12265330 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/265330
Method and apparatus for testing logic circuit designs Nov 4, 2008 Issued
Array ( [id] => 5445585 [patent_doc_number] => 20090046811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'TRANSMITTING APPARATUS, RECEIVING APPARATUS, TRANSMISSION METHOD, AND RECEPTION METHOD' [patent_app_type] => utility [patent_app_number] => 12/199518 [patent_app_country] => US [patent_app_date] => 2008-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7550 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20090046811.pdf [firstpage_image] =>[orig_patent_app_number] => 12199518 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/199518
Transmitting apparatus, receiving apparatus, transmission method, and reception method Aug 26, 2008 Issued
Array ( [id] => 5292164 [patent_doc_number] => 20090024894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-22 [patent_title] => 'SYSTEM AND METHOD FOR PREDICTING IWARX AND STWCX INSTRUCTIONS IN TEST PATTERN GENERATION AND SIMULATION FOR PROCESSOR DESIGN VERIFICATION/VALIDATION IN INTERRUPT MODE' [patent_app_type] => utility [patent_app_number] => 12/172628 [patent_app_country] => US [patent_app_date] => 2008-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 11734 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20090024894.pdf [firstpage_image] =>[orig_patent_app_number] => 12172628 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/172628
Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt mode Jul 13, 2008 Issued
Array ( [id] => 6462037 [patent_doc_number] => 20100090718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'SEMICONDUCTOR DEVICE, AND DEVELOPMENT SUPPORTING DEVICE' [patent_app_type] => utility [patent_app_number] => 12/598011 [patent_app_country] => US [patent_app_date] => 2008-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 14192 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20100090718.pdf [firstpage_image] =>[orig_patent_app_number] => 12598011 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/598011
SEMICONDUCTOR DEVICE, AND DEVELOPMENT SUPPORTING DEVICE Jun 8, 2008 Abandoned
Array ( [id] => 4700283 [patent_doc_number] => 20080222467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'METHOD OF CONTROLLING A TEST MODE OF CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/123191 [patent_app_country] => US [patent_app_date] => 2008-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2521 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20080222467.pdf [firstpage_image] =>[orig_patent_app_number] => 12123191 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/123191
Method of controlling a test mode of a circuit May 18, 2008 Issued
Array ( [id] => 8931 [patent_doc_number] => 07818634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Detecting method and system for consistency of link scrambling configuration' [patent_app_type] => utility [patent_app_number] => 12/122315 [patent_app_country] => US [patent_app_date] => 2008-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3661 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/818/07818634.pdf [firstpage_image] =>[orig_patent_app_number] => 12122315 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/122315
Detecting method and system for consistency of link scrambling configuration May 15, 2008 Issued
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