Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5356457 [patent_doc_number] => 20090187801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'METHOD AND SYSTEM TO PERFORM AT-SPEED TESTING' [patent_app_type] => utility [patent_app_number] => 12/016044 [patent_app_country] => US [patent_app_date] => 2008-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4678 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20090187801.pdf [firstpage_image] =>[orig_patent_app_number] => 12016044 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/016044
METHOD AND SYSTEM TO PERFORM AT-SPEED TESTING Jan 16, 2008 Abandoned
Array ( [id] => 4753994 [patent_doc_number] => 20080162070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'FAILURE ANALYSIS AND TESTING OF SEMI-CONDUCTOR DEVICES USING INTELLIGENT SOFTWARE ON AUTOMATED TEST EQUIPMENT (ATE)' [patent_app_type] => utility [patent_app_number] => 11/964920 [patent_app_country] => US [patent_app_date] => 2007-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 20782 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20080162070.pdf [firstpage_image] =>[orig_patent_app_number] => 11964920 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/964920
Failure analysis and testing of semi-conductor devices using intelligent software on automated test equipment (ATE) Dec 26, 2007 Issued
Array ( [id] => 5351551 [patent_doc_number] => 20090006912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'Semiconductor memory device having burn-in test mode and method for driving the same' [patent_app_type] => utility [patent_app_number] => 12/005445 [patent_app_country] => US [patent_app_date] => 2007-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6358 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20090006912.pdf [firstpage_image] =>[orig_patent_app_number] => 12005445 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/005445
Semiconductor memory device having burn-in test mode and method for driving the same Dec 25, 2007 Issued
Array ( [id] => 200953 [patent_doc_number] => 07640474 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'System and method for input/output characterization' [patent_app_type] => utility [patent_app_number] => 11/962297 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6971 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/640/07640474.pdf [firstpage_image] =>[orig_patent_app_number] => 11962297 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/962297
System and method for input/output characterization Dec 20, 2007 Issued
Array ( [id] => 48956 [patent_doc_number] => 07779317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Test control circuit and reference voltage generating circuit having the same' [patent_app_type] => utility [patent_app_number] => 11/963463 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3506 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/779/07779317.pdf [firstpage_image] =>[orig_patent_app_number] => 11963463 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/963463
Test control circuit and reference voltage generating circuit having the same Dec 20, 2007 Issued
Array ( [id] => 5548227 [patent_doc_number] => 20090158104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'METHOD AND APPARATUS FOR MEMORY AC TIMING MEASUREMENT' [patent_app_type] => utility [patent_app_number] => 11/958710 [patent_app_country] => US [patent_app_date] => 2007-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3632 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158104.pdf [firstpage_image] =>[orig_patent_app_number] => 11958710 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958710
Method and apparatus for memory AC timing measurement Dec 17, 2007 Issued
Array ( [id] => 5548225 [patent_doc_number] => 20090158102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'Methods, devices, and systems for experiencing reduced unequal testing degradation' [patent_app_type] => utility [patent_app_number] => 12/002830 [patent_app_country] => US [patent_app_date] => 2007-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2928 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158102.pdf [firstpage_image] =>[orig_patent_app_number] => 12002830 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/002830
Methods, devices, and systems for experiencing reduced unequal testing degradation Dec 17, 2007 Issued
Array ( [id] => 5548207 [patent_doc_number] => 20090158084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'Redundant Bit Patterns for Column Defects Coding' [patent_app_type] => utility [patent_app_number] => 11/958200 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4093 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158084.pdf [firstpage_image] =>[orig_patent_app_number] => 11958200 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958200
Redundant bit patterns for column defects coding Dec 16, 2007 Issued
Array ( [id] => 5548230 [patent_doc_number] => 20090158107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'SYSTEM-ON-CHIP WITH MASTER/SLAVE DEBUG INTERFACE' [patent_app_type] => utility [patent_app_number] => 11/954362 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1970 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158107.pdf [firstpage_image] =>[orig_patent_app_number] => 11954362 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/954362
System-on-chip with master/slave debug interface Dec 11, 2007 Issued
Array ( [id] => 4825740 [patent_doc_number] => 20080228989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'METHOD AND DEVICE FOR SECURING THE READING OF A MEMORY' [patent_app_type] => utility [patent_app_number] => 11/954606 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7143 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20080228989.pdf [firstpage_image] =>[orig_patent_app_number] => 11954606 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/954606
Method and device for securing the reading of a memory Dec 11, 2007 Issued
Array ( [id] => 5424276 [patent_doc_number] => 20090150732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR INTEGRATED CIRCUIT RECOVERY TESTING USING SIMULATION CHECKPOINTS' [patent_app_type] => utility [patent_app_number] => 11/951431 [patent_app_country] => US [patent_app_date] => 2007-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4018 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20090150732.pdf [firstpage_image] =>[orig_patent_app_number] => 11951431 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/951431
Method, system, and computer program product for integrated circuit recovery testing using simulation checkpoints Dec 5, 2007 Issued
Array ( [id] => 4500097 [patent_doc_number] => 07904766 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-08 [patent_title] => 'Statistical yield of a system-on-a-chip' [patent_app_type] => utility [patent_app_number] => 11/951338 [patent_app_country] => US [patent_app_date] => 2007-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3917 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/904/07904766.pdf [firstpage_image] =>[orig_patent_app_number] => 11951338 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/951338
Statistical yield of a system-on-a-chip Dec 5, 2007 Issued
Array ( [id] => 5411870 [patent_doc_number] => 20090125769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'ON-CHIP CIRCUIT FOR TRANSITION DELAY FAULT TEST PATTERN GENERATION WITH LAUNCH OFF SHIFT' [patent_app_type] => utility [patent_app_number] => 11/939573 [patent_app_country] => US [patent_app_date] => 2007-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4089 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20090125769.pdf [firstpage_image] =>[orig_patent_app_number] => 11939573 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/939573
On-chip circuit for transition delay fault test pattern generation with launch off shift Nov 13, 2007 Issued
Array ( [id] => 5411871 [patent_doc_number] => 20090125770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'SCAN BASED COMPUTATION OF A SIGNATURE CONCURRENTLY WITH FUNCTIONAL OPERATION' [patent_app_type] => utility [patent_app_number] => 11/940043 [patent_app_country] => US [patent_app_date] => 2007-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5385 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20090125770.pdf [firstpage_image] =>[orig_patent_app_number] => 11940043 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/940043
Scan based computation of a signature concurrently with functional operation Nov 13, 2007 Issued
Array ( [id] => 5411849 [patent_doc_number] => 20090125748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'Methods for the Support of JTAG for Source Synchronous Interfaces' [patent_app_type] => utility [patent_app_number] => 11/939751 [patent_app_country] => US [patent_app_date] => 2007-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1373 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20090125748.pdf [firstpage_image] =>[orig_patent_app_number] => 11939751 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/939751
Methods for the support of JTAG for source synchronous interfaces Nov 13, 2007 Issued
Array ( [id] => 97442 [patent_doc_number] => 07739568 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-15 [patent_title] => 'Scan testing system for circuits under test' [patent_app_type] => utility [patent_app_number] => 11/983856 [patent_app_country] => US [patent_app_date] => 2007-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 12725 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/739/07739568.pdf [firstpage_image] =>[orig_patent_app_number] => 11983856 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/983856
Scan testing system for circuits under test Nov 12, 2007 Issued
Array ( [id] => 5411864 [patent_doc_number] => 20090125763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'PROGRAMMABLE MEMORY BUILT-IN SELF-TEST CIRCUIT AND CLOCK SWITCHING CIRCUIT THEREOF' [patent_app_type] => utility [patent_app_number] => 11/939282 [patent_app_country] => US [patent_app_date] => 2007-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5685 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20090125763.pdf [firstpage_image] =>[orig_patent_app_number] => 11939282 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/939282
Programmable memory built-in self-test circuit and clock switching circuit thereof Nov 12, 2007 Issued
Array ( [id] => 58282 [patent_doc_number] => 07774662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Method and structure for picosecond-imaging-circuit-analysis based built-in-self-test diagnostic' [patent_app_type] => utility [patent_app_number] => 11/927030 [patent_app_country] => US [patent_app_date] => 2007-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 6360 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/774/07774662.pdf [firstpage_image] =>[orig_patent_app_number] => 11927030 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/927030
Method and structure for picosecond-imaging-circuit-analysis based built-in-self-test diagnostic Oct 28, 2007 Issued
Array ( [id] => 237739 [patent_doc_number] => 07596728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Built-in self repair circuit for a multi-port memory and method thereof' [patent_app_type] => utility [patent_app_number] => 11/870169 [patent_app_country] => US [patent_app_date] => 2007-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 6682 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/596/07596728.pdf [firstpage_image] =>[orig_patent_app_number] => 11870169 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/870169
Built-in self repair circuit for a multi-port memory and method thereof Oct 9, 2007 Issued
Array ( [id] => 4511113 [patent_doc_number] => 07949908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'Memory repair system and method' [patent_app_type] => utility [patent_app_number] => 11/869308 [patent_app_country] => US [patent_app_date] => 2007-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 10372 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/949/07949908.pdf [firstpage_image] =>[orig_patent_app_number] => 11869308 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/869308
Memory repair system and method Oct 8, 2007 Issued
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