
Christine Trinh Le Tu
Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784 |
| Total Applications | 1748 |
| Issued Applications | 1571 |
| Pending Applications | 27 |
| Abandoned Applications | 152 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5356457
[patent_doc_number] => 20090187801
[patent_country] => US
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[patent_issue_date] => 2009-07-23
[patent_title] => 'METHOD AND SYSTEM TO PERFORM AT-SPEED TESTING'
[patent_app_type] => utility
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[pdf_file] => publications/A1/0187/20090187801.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/016044 | METHOD AND SYSTEM TO PERFORM AT-SPEED TESTING | Jan 16, 2008 | Abandoned |
Array
(
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[patent_doc_number] => 20080162070
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[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'FAILURE ANALYSIS AND TESTING OF SEMI-CONDUCTOR DEVICES USING INTELLIGENT SOFTWARE ON AUTOMATED TEST EQUIPMENT (ATE)'
[patent_app_type] => utility
[patent_app_number] => 11/964920
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/964920 | Failure analysis and testing of semi-conductor devices using intelligent software on automated test equipment (ATE) | Dec 26, 2007 | Issued |
Array
(
[id] => 5351551
[patent_doc_number] => 20090006912
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-01-01
[patent_title] => 'Semiconductor memory device having burn-in test mode and method for driving the same'
[patent_app_type] => utility
[patent_app_number] => 12/005445
[patent_app_country] => US
[patent_app_date] => 2007-12-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/005445 | Semiconductor memory device having burn-in test mode and method for driving the same | Dec 25, 2007 | Issued |
Array
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[id] => 200953
[patent_doc_number] => 07640474
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[patent_issue_date] => 2009-12-29
[patent_title] => 'System and method for input/output characterization'
[patent_app_type] => utility
[patent_app_number] => 11/962297
[patent_app_country] => US
[patent_app_date] => 2007-12-21
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Array
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[patent_title] => 'Test control circuit and reference voltage generating circuit having the same'
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[patent_app_date] => 2007-12-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/963463 | Test control circuit and reference voltage generating circuit having the same | Dec 20, 2007 | Issued |
Array
(
[id] => 5548227
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[patent_issue_date] => 2009-06-18
[patent_title] => 'METHOD AND APPARATUS FOR MEMORY AC TIMING MEASUREMENT'
[patent_app_type] => utility
[patent_app_number] => 11/958710
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/958710 | Method and apparatus for memory AC timing measurement | Dec 17, 2007 | Issued |
Array
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[patent_title] => 'Methods, devices, and systems for experiencing reduced unequal testing degradation'
[patent_app_type] => utility
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Array
(
[id] => 5548207
[patent_doc_number] => 20090158084
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-18
[patent_title] => 'Redundant Bit Patterns for Column Defects Coding'
[patent_app_type] => utility
[patent_app_number] => 11/958200
[patent_app_country] => US
[patent_app_date] => 2007-12-17
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[firstpage_image] =>[orig_patent_app_number] => 11958200
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/958200 | Redundant bit patterns for column defects coding | Dec 16, 2007 | Issued |
Array
(
[id] => 5548230
[patent_doc_number] => 20090158107
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[patent_issue_date] => 2009-06-18
[patent_title] => 'SYSTEM-ON-CHIP WITH MASTER/SLAVE DEBUG INTERFACE'
[patent_app_type] => utility
[patent_app_number] => 11/954362
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[patent_app_date] => 2007-12-12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/954362 | System-on-chip with master/slave debug interface | Dec 11, 2007 | Issued |
Array
(
[id] => 4825740
[patent_doc_number] => 20080228989
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[patent_kind] => A1
[patent_issue_date] => 2008-09-18
[patent_title] => 'METHOD AND DEVICE FOR SECURING THE READING OF A MEMORY'
[patent_app_type] => utility
[patent_app_number] => 11/954606
[patent_app_country] => US
[patent_app_date] => 2007-12-12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/954606 | Method and device for securing the reading of a memory | Dec 11, 2007 | Issued |
Array
(
[id] => 5424276
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[patent_title] => 'METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR INTEGRATED CIRCUIT RECOVERY TESTING USING SIMULATION CHECKPOINTS'
[patent_app_type] => utility
[patent_app_number] => 11/951431
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/951431 | Method, system, and computer program product for integrated circuit recovery testing using simulation checkpoints | Dec 5, 2007 | Issued |
Array
(
[id] => 4500097
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[patent_title] => 'Statistical yield of a system-on-a-chip'
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Array
(
[id] => 5411870
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[patent_title] => 'ON-CHIP CIRCUIT FOR TRANSITION DELAY FAULT TEST PATTERN GENERATION WITH LAUNCH OFF SHIFT'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/939573 | On-chip circuit for transition delay fault test pattern generation with launch off shift | Nov 13, 2007 | Issued |
Array
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Array
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Array
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Array
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