Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5442858 [patent_doc_number] => 20090094497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'DATA INVERSION REGISTER TECHNIQUE FOR INTEGRATED CIRCUIT MEMORY TESTING' [patent_app_type] => utility [patent_app_number] => 11/868509 [patent_app_country] => US [patent_app_date] => 2007-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3080 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20090094497.pdf [firstpage_image] =>[orig_patent_app_number] => 11868509 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/868509
Data inversion register technique for integrated circuit memory testing Oct 6, 2007 Issued
Array ( [id] => 5439707 [patent_doc_number] => 20090091346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'CIRCUITS AND METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRONIC MEMORY CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/866502 [patent_app_country] => US [patent_app_date] => 2007-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8079 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20090091346.pdf [firstpage_image] =>[orig_patent_app_number] => 11866502 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/866502
Circuits and methods for characterizing device variation in electronic memory circuits Oct 2, 2007 Issued
Array ( [id] => 5442857 [patent_doc_number] => 20090094496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'System and Method for Improved LBIST Power and Run Time' [patent_app_type] => utility [patent_app_number] => 11/866787 [patent_app_country] => US [patent_app_date] => 2007-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4951 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20090094496.pdf [firstpage_image] =>[orig_patent_app_number] => 11866787 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/866787
System and method for improved LBIST power and run time Oct 2, 2007 Issued
Array ( [id] => 4693895 [patent_doc_number] => 20080086666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'ANALYZER' [patent_app_type] => utility [patent_app_number] => 11/866595 [patent_app_country] => US [patent_app_date] => 2007-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 18880 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20080086666.pdf [firstpage_image] =>[orig_patent_app_number] => 11866595 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/866595
Analyzer Oct 2, 2007 Issued
Array ( [id] => 146896 [patent_doc_number] => 07694201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-06 [patent_title] => 'Semiconductor testing device having test result sending back to generate second data' [patent_app_type] => utility [patent_app_number] => 11/858374 [patent_app_country] => US [patent_app_date] => 2007-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 14693 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/694/07694201.pdf [firstpage_image] =>[orig_patent_app_number] => 11858374 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/858374
Semiconductor testing device having test result sending back to generate second data Sep 19, 2007 Issued
Array ( [id] => 58300 [patent_doc_number] => 07774670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Method and apparatus for dynamically determining tester recipes' [patent_app_type] => utility [patent_app_number] => 11/853304 [patent_app_country] => US [patent_app_date] => 2007-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3560 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/774/07774670.pdf [firstpage_image] =>[orig_patent_app_number] => 11853304 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/853304
Method and apparatus for dynamically determining tester recipes Sep 10, 2007 Issued
Array ( [id] => 48961 [patent_doc_number] => 07779322 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-08-17 [patent_title] => 'Compacting test responses using X-driven compactor' [patent_app_type] => utility [patent_app_number] => 11/898070 [patent_app_country] => US [patent_app_date] => 2007-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5267 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/779/07779322.pdf [firstpage_image] =>[orig_patent_app_number] => 11898070 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/898070
Compacting test responses using X-driven compactor Sep 6, 2007 Issued
Array ( [id] => 5312050 [patent_doc_number] => 20090019331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'Integrated circuit for a data transmission system and receiving device of a data transmission system' [patent_app_type] => utility [patent_app_number] => 11/850639 [patent_app_country] => US [patent_app_date] => 2007-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3487 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20090019331.pdf [firstpage_image] =>[orig_patent_app_number] => 11850639 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/850639
Integrated circuit for a data transmission system and receiving device of a data transmission system Sep 4, 2007 Issued
Array ( [id] => 4592869 [patent_doc_number] => 07853845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'Circuit and method for integrated circuit configuration' [patent_app_type] => utility [patent_app_number] => 11/845662 [patent_app_country] => US [patent_app_date] => 2007-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2872 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/853/07853845.pdf [firstpage_image] =>[orig_patent_app_number] => 11845662 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/845662
Circuit and method for integrated circuit configuration Aug 26, 2007 Issued
Array ( [id] => 128202 [patent_doc_number] => 07707471 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Method of defining fault pattern of equipment and method of monitoring equipment using the same' [patent_app_type] => utility [patent_app_number] => 11/892090 [patent_app_country] => US [patent_app_date] => 2007-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4670 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/707/07707471.pdf [firstpage_image] =>[orig_patent_app_number] => 11892090 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/892090
Method of defining fault pattern of equipment and method of monitoring equipment using the same Aug 19, 2007 Issued
Array ( [id] => 5012711 [patent_doc_number] => 20070283190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'RUNTIME RECONFIGURATION OF RECONFIGURABLE CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/840853 [patent_app_country] => US [patent_app_date] => 2007-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6080 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20070283190.pdf [firstpage_image] =>[orig_patent_app_number] => 11840853 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/840853
Runtime reconfiguration of reconfigurable circuits Aug 16, 2007 Issued
Array ( [id] => 5362987 [patent_doc_number] => 20090037781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'CORRECTING INTERMITTENT ERRORS IN DATA STORAGE STRUCTURES' [patent_app_type] => utility [patent_app_number] => 11/833784 [patent_app_country] => US [patent_app_date] => 2007-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2277 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20090037781.pdf [firstpage_image] =>[orig_patent_app_number] => 11833784 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/833784
Correcting intermittent errors in data storage structures Aug 2, 2007 Issued
Array ( [id] => 5200791 [patent_doc_number] => 20070300109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'HIGH SPEED INTERCONNECT CIRCUIT TEST METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/833088 [patent_app_country] => US [patent_app_date] => 2007-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13588 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20070300109.pdf [firstpage_image] =>[orig_patent_app_number] => 11833088 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/833088
Propagation test strobe circuitry with boundary scan circuitry Aug 1, 2007 Issued
Array ( [id] => 5292162 [patent_doc_number] => 20090024892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-22 [patent_title] => 'System and Method of Testing using Test Pattern Re-Execution in Varying Timing Scenarios for Processor Design Verification and Validation' [patent_app_type] => utility [patent_app_number] => 11/779395 [patent_app_country] => US [patent_app_date] => 2007-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 11332 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20090024892.pdf [firstpage_image] =>[orig_patent_app_number] => 11779395 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/779395
System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validation Jul 17, 2007 Issued
Array ( [id] => 5292159 [patent_doc_number] => 20090024889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-22 [patent_title] => 'INTEGRATED CIRCUIT HAVING BUILT-IN SELF-TEST FEATURES' [patent_app_type] => utility [patent_app_number] => 11/779354 [patent_app_country] => US [patent_app_date] => 2007-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8901 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20090024889.pdf [firstpage_image] =>[orig_patent_app_number] => 11779354 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/779354
Integrated circuit having built-in self-test features Jul 17, 2007 Issued
Array ( [id] => 5292156 [patent_doc_number] => 20090024886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-22 [patent_title] => 'System and Method for Predicting lwarx and stwcx Instructions in Test Pattern Generation and Simulation for Processor Design Verification and Validation' [patent_app_type] => utility [patent_app_number] => 11/779390 [patent_app_country] => US [patent_app_date] => 2007-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 11335 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20090024886.pdf [firstpage_image] =>[orig_patent_app_number] => 11779390 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/779390
System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validation Jul 17, 2007 Issued
Array ( [id] => 5292143 [patent_doc_number] => 20090024873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-22 [patent_title] => 'System and Method for Increasing Error Checking Performance by Calculating CRC Calculations After Multiple Test Patterns for Processor Design Verification and Validation' [patent_app_type] => utility [patent_app_number] => 11/779385 [patent_app_country] => US [patent_app_date] => 2007-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 11413 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20090024873.pdf [firstpage_image] =>[orig_patent_app_number] => 11779385 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/779385
System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validation Jul 17, 2007 Issued
Array ( [id] => 5292161 [patent_doc_number] => 20090024891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-22 [patent_title] => 'System and Method for Pseudo-Random Test Pattern Memory Allocation for Processor Design Verification and Validation' [patent_app_type] => utility [patent_app_number] => 11/779394 [patent_app_country] => US [patent_app_date] => 2007-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 11381 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20090024891.pdf [firstpage_image] =>[orig_patent_app_number] => 11779394 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/779394
System and method for pseudo-random test pattern memory allocation for processor design verification and validation Jul 17, 2007 Issued
Array ( [id] => 8937 [patent_doc_number] => 07818637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Apparatus for formatting information storage medium' [patent_app_type] => utility [patent_app_number] => 11/779379 [patent_app_country] => US [patent_app_date] => 2007-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 14044 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/818/07818637.pdf [firstpage_image] =>[orig_patent_app_number] => 11779379 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/779379
Apparatus for formatting information storage medium Jul 17, 2007 Issued
Array ( [id] => 4966870 [patent_doc_number] => 20080109690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'TEST SYSTEM EMPLOYING TEST CONTROLLER COMPRESSING DATA, DATA COMPRESSING CIRCUIT AND TEST METHOD' [patent_app_type] => utility [patent_app_number] => 11/778161 [patent_app_country] => US [patent_app_date] => 2007-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3746 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20080109690.pdf [firstpage_image] =>[orig_patent_app_number] => 11778161 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/778161
Test system employing test controller compressing data, data compressing circuit and test method Jul 15, 2007 Issued
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