Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 258195 [patent_doc_number] => 07577883 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-18 [patent_title] => 'Data transmission speed test system and method' [patent_app_type] => utility [patent_app_number] => 11/778073 [patent_app_country] => US [patent_app_date] => 2007-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2099 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/577/07577883.pdf [firstpage_image] =>[orig_patent_app_number] => 11778073 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/778073
Data transmission speed test system and method Jul 15, 2007 Issued
Array ( [id] => 5308849 [patent_doc_number] => 20090016130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'MEMORY DEVICE AND METHOD OF TESTING A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/777189 [patent_app_country] => US [patent_app_date] => 2007-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8930 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20090016130.pdf [firstpage_image] =>[orig_patent_app_number] => 11777189 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/777189
MEMORY DEVICE AND METHOD OF TESTING A MEMORY DEVICE Jul 11, 2007 Abandoned
Array ( [id] => 4731748 [patent_doc_number] => 20080048726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Signal Integrity Measurement Systems and Methods Using a Predominantly Digital Time-Base Generator' [patent_app_type] => utility [patent_app_number] => 11/776825 [patent_app_country] => US [patent_app_date] => 2007-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10664 [patent_no_of_claims] => 77 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20080048726.pdf [firstpage_image] =>[orig_patent_app_number] => 11776825 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/776825
Signal integrity measurement systems and methods using a predominantly digital time-base generator Jul 11, 2007 Issued
Array ( [id] => 8235570 [patent_doc_number] => 08201032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-12 [patent_title] => 'Generalized BIST for multiport memories' [patent_app_type] => utility [patent_app_number] => 11/775956 [patent_app_country] => US [patent_app_date] => 2007-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6940 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/201/08201032.pdf [firstpage_image] =>[orig_patent_app_number] => 11775956 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/775956
Generalized BIST for multiport memories Jul 10, 2007 Issued
Array ( [id] => 5248961 [patent_doc_number] => 20070245195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'METHOD, SYSTEM AND PROGRAM PRODUCT FOR BOUNDARY I/O TESTING EMPLOYING A LOGIC BUILT-IN SELF-TEST OF AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/764502 [patent_app_country] => US [patent_app_date] => 2007-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9201 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20070245195.pdf [firstpage_image] =>[orig_patent_app_number] => 11764502 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/764502
Method, system and program product for boundary I/O testing employing a logic built-in self-test of an integrated circuit Jun 17, 2007 Issued
Array ( [id] => 5127754 [patent_doc_number] => 20070240025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'METHOD, SYSTEM, AND PROGRAM PRODUCT FOR CONTROLLING TEST DATA OF A LOGIC BUILT-IN SELF-TEST OF AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/762889 [patent_app_country] => US [patent_app_date] => 2007-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9291 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20070240025.pdf [firstpage_image] =>[orig_patent_app_number] => 11762889 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/762889
Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit Jun 13, 2007 Issued
Array ( [id] => 5064792 [patent_doc_number] => 20070226434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'DATA RECOVERY IN A MEMORY SYSTEM USING TRACKING CELLS' [patent_app_type] => utility [patent_app_number] => 11/752024 [patent_app_country] => US [patent_app_date] => 2007-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12911 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20070226434.pdf [firstpage_image] =>[orig_patent_app_number] => 11752024 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/752024
Data recovery in a memory system using tracking cells May 21, 2007 Issued
Array ( [id] => 832692 [patent_doc_number] => 07401280 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-15 [patent_title] => 'Self-verification of configuration memory in programmable logic devices' [patent_app_type] => utility [patent_app_number] => 11/750790 [patent_app_country] => US [patent_app_date] => 2007-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3616 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/401/07401280.pdf [firstpage_image] =>[orig_patent_app_number] => 11750790 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/750790
Self-verification of configuration memory in programmable logic devices May 17, 2007 Issued
Array ( [id] => 5167222 [patent_doc_number] => 20070288811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'SYSTEM AND METHOD FOR TESTING A DATA STORAGE DEVICE WITHOUT REVEALING MEMORY CONTENT' [patent_app_type] => utility [patent_app_number] => 11/741992 [patent_app_country] => US [patent_app_date] => 2007-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 3372 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20070288811.pdf [firstpage_image] =>[orig_patent_app_number] => 11741992 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/741992
System and method for testing a data storage device without revealing memory content Apr 29, 2007 Issued
Array ( [id] => 5212161 [patent_doc_number] => 20070250745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'METHOD AND SYSTEM FOR TESTING A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/735176 [patent_app_country] => US [patent_app_date] => 2007-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4504 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20070250745.pdf [firstpage_image] =>[orig_patent_app_number] => 11735176 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/735176
METHOD AND SYSTEM FOR TESTING A MEMORY DEVICE Apr 12, 2007 Abandoned
Array ( [id] => 245166 [patent_doc_number] => 07590910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Tap and linking module for scan access of multiple cores with IEEE 1149.1 test access ports' [patent_app_type] => utility [patent_app_number] => 11/691600 [patent_app_country] => US [patent_app_date] => 2007-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5834 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/590/07590910.pdf [firstpage_image] =>[orig_patent_app_number] => 11691600 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/691600
Tap and linking module for scan access of multiple cores with IEEE 1149.1 test access ports Mar 26, 2007 Issued
Array ( [id] => 4741896 [patent_doc_number] => 20080235549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'TEST APPARATUS AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 11/689489 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11200 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20080235549.pdf [firstpage_image] =>[orig_patent_app_number] => 11689489 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/689489
Test apparatus and electronic device for generating test signal by using repeated interval in a test instruction stream Mar 20, 2007 Issued
Array ( [id] => 4741845 [patent_doc_number] => 20080235498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'TEST APPARATUS AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 11/689503 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9763 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20080235498.pdf [firstpage_image] =>[orig_patent_app_number] => 11689503 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/689503
Test apparatus for updating a value of the bit position in result register by executing a result register update instruction with predetermined value to generate test pattern Mar 20, 2007 Issued
Array ( [id] => 4741895 [patent_doc_number] => 20080235548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'TEST APPARATUS, AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 11/688879 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8665 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20080235548.pdf [firstpage_image] =>[orig_patent_app_number] => 11688879 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/688879
Test apparatus and electronic device for generating test signal to a device under test Mar 20, 2007 Issued
Array ( [id] => 4462600 [patent_doc_number] => 07895487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Scan chain diagnostics using logic paths' [patent_app_type] => utility [patent_app_number] => 11/687003 [patent_app_country] => US [patent_app_date] => 2007-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5228 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/895/07895487.pdf [firstpage_image] =>[orig_patent_app_number] => 11687003 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/687003
Scan chain diagnostics using logic paths Mar 15, 2007 Issued
Array ( [id] => 69058 [patent_doc_number] => 07761751 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-07-20 [patent_title] => 'Test and diagnosis of semiconductors' [patent_app_type] => utility [patent_app_number] => 11/708824 [patent_app_country] => US [patent_app_date] => 2007-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5280 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/761/07761751.pdf [firstpage_image] =>[orig_patent_app_number] => 11708824 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/708824
Test and diagnosis of semiconductors Feb 19, 2007 Issued
Array ( [id] => 7689900 [patent_doc_number] => 20070234133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Device and method for testing memory access time using PLL' [patent_app_type] => utility [patent_app_number] => 11/706996 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3873 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20070234133.pdf [firstpage_image] =>[orig_patent_app_number] => 11706996 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/706996
Device and method for testing memory access time using PLL Feb 15, 2007 Abandoned
Array ( [id] => 69074 [patent_doc_number] => 07761755 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-07-20 [patent_title] => 'Circuit for and method of testing for faults in a programmable logic device' [patent_app_type] => utility [patent_app_number] => 11/707360 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5434 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/761/07761755.pdf [firstpage_image] =>[orig_patent_app_number] => 11707360 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/707360
Circuit for and method of testing for faults in a programmable logic device Feb 15, 2007 Issued
Array ( [id] => 4649250 [patent_doc_number] => 20080036505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 11/675567 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7852 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20080036505.pdf [firstpage_image] =>[orig_patent_app_number] => 11675567 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/675567
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Feb 14, 2007 Abandoned
Array ( [id] => 175661 [patent_doc_number] => 07661044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-09 [patent_title] => 'Method, apparatus and program product to concurrently detect, repair, verify and isolate memory failures' [patent_app_type] => utility [patent_app_number] => 11/673630 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2199 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/661/07661044.pdf [firstpage_image] =>[orig_patent_app_number] => 11673630 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/673630
Method, apparatus and program product to concurrently detect, repair, verify and isolate memory failures Feb 11, 2007 Issued
Menu