Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7689877 [patent_doc_number] => 20070234156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'ELECTRONIC CIRCUIT COMPRISING A TEST MODE SECURED BY THE BREAKING OF A TEST CHAIN, AND ASSOCIATED ELECTRONIC CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/673911 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3855 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20070234156.pdf [firstpage_image] =>[orig_patent_app_number] => 11673911 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/673911
Electronic circuit comprising a test mode secured by the breaking of a test chain, and associated electronic circuit Feb 11, 2007 Issued
Array ( [id] => 5178685 [patent_doc_number] => 20070179745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'Failure Analysis and Testing of Semi-conductor Devices using Intelligent Software on Automated Test Equipment (ATE)' [patent_app_type] => utility [patent_app_number] => 11/670031 [patent_app_country] => US [patent_app_date] => 2007-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 20464 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20070179745.pdf [firstpage_image] =>[orig_patent_app_number] => 11670031 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/670031
Failure analysis and testing of semi-conductor devices using intelligent software on automated test equipment (ATE) Jan 31, 2007 Issued
Array ( [id] => 4592867 [patent_doc_number] => 07853843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'Method and system for testing chips' [patent_app_type] => utility [patent_app_number] => 11/668440 [patent_app_country] => US [patent_app_date] => 2007-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1745 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/853/07853843.pdf [firstpage_image] =>[orig_patent_app_number] => 11668440 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/668440
Method and system for testing chips Jan 28, 2007 Issued
Array ( [id] => 4979138 [patent_doc_number] => 20070220373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'METHOD FOR PERFORMING A DEFECTIVE-AREA MANAGEMENT IN AN OPTICAL MEDIA' [patent_app_type] => utility [patent_app_number] => 11/612075 [patent_app_country] => US [patent_app_date] => 2006-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4672 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20070220373.pdf [firstpage_image] =>[orig_patent_app_number] => 11612075 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/612075
Method for performing a defective-area management in an optical media Dec 17, 2006 Issued
Array ( [id] => 5118311 [patent_doc_number] => 20070140025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'METHOD AND APPARATUS FOR TESTING A FULLY BUFFERED MEMORY MODULE' [patent_app_type] => utility [patent_app_number] => 11/611390 [patent_app_country] => US [patent_app_date] => 2006-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2989 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20070140025.pdf [firstpage_image] =>[orig_patent_app_number] => 11611390 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/611390
Method and apparatus for testing a fully buffered memory module Dec 14, 2006 Issued
Array ( [id] => 248889 [patent_doc_number] => 07587650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-08 [patent_title] => 'Clock jitter detector' [patent_app_type] => utility [patent_app_number] => 11/636101 [patent_app_country] => US [patent_app_date] => 2006-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5114 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/587/07587650.pdf [firstpage_image] =>[orig_patent_app_number] => 11636101 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/636101
Clock jitter detector Dec 7, 2006 Issued
Array ( [id] => 305862 [patent_doc_number] => 07536621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Quantized data-dependent jitter injection using discrete samples' [patent_app_type] => utility [patent_app_number] => 11/608460 [patent_app_country] => US [patent_app_date] => 2006-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7385 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/536/07536621.pdf [firstpage_image] =>[orig_patent_app_number] => 11608460 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/608460
Quantized data-dependent jitter injection using discrete samples Dec 7, 2006 Issued
Array ( [id] => 5238331 [patent_doc_number] => 20070130488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'Semiconductor device and data storage apparatus' [patent_app_type] => utility [patent_app_number] => 11/607029 [patent_app_country] => US [patent_app_date] => 2006-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 12738 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20070130488.pdf [firstpage_image] =>[orig_patent_app_number] => 11607029 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/607029
Semiconductor device and data storage apparatus Nov 30, 2006 Issued
Array ( [id] => 5221485 [patent_doc_number] => 20070162797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'Test device and method for testing electronic devices' [patent_app_type] => utility [patent_app_number] => 11/603633 [patent_app_country] => US [patent_app_date] => 2006-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6962 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20070162797.pdf [firstpage_image] =>[orig_patent_app_number] => 11603633 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/603633
Test device and method for testing electronic devices Nov 21, 2006 Abandoned
Array ( [id] => 5064927 [patent_doc_number] => 20070226569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'Film-type semiconductor package and method using test pads shared by output channels, and test device, semiconductor device and method using patterns shared by test channels' [patent_app_type] => utility [patent_app_number] => 11/602749 [patent_app_country] => US [patent_app_date] => 2006-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5666 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20070226569.pdf [firstpage_image] =>[orig_patent_app_number] => 11602749 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/602749
Film-type semiconductor package and method using test pads shared by output channels, and test device, semiconductor device and method using patterns shared by test channels Nov 20, 2006 Issued
Array ( [id] => 7694220 [patent_doc_number] => 20080120524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-22 [patent_title] => 'Method and apparatus for monitoring bit-error rate' [patent_app_type] => utility [patent_app_number] => 11/602349 [patent_app_country] => US [patent_app_date] => 2006-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3938 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20080120524.pdf [firstpage_image] =>[orig_patent_app_number] => 11602349 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/602349
Method and apparatus for monitoring bit-error rate Nov 20, 2006 Issued
Array ( [id] => 4900445 [patent_doc_number] => 20080120059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-22 [patent_title] => 'Test apparatus and test method' [patent_app_type] => utility [patent_app_number] => 11/600676 [patent_app_country] => US [patent_app_date] => 2006-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6511 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20080120059.pdf [firstpage_image] =>[orig_patent_app_number] => 11600676 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/600676
Test apparatus and test method Nov 15, 2006 Issued
Array ( [id] => 297923 [patent_doc_number] => 07543202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-02 [patent_title] => 'Test apparatus, adjustment apparatus, adjustment method and adjustment program' [patent_app_type] => utility [patent_app_number] => 11/595815 [patent_app_country] => US [patent_app_date] => 2006-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13347 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/543/07543202.pdf [firstpage_image] =>[orig_patent_app_number] => 11595815 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/595815
Test apparatus, adjustment apparatus, adjustment method and adjustment program Nov 8, 2006 Issued
Array ( [id] => 8149347 [patent_doc_number] => 08166361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-24 [patent_title] => 'Integrated circuit testing module configured for set-up and hold time testing' [patent_app_type] => utility [patent_app_number] => 11/552944 [patent_app_country] => US [patent_app_date] => 2006-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 43 [patent_no_of_words] => 21969 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/166/08166361.pdf [firstpage_image] =>[orig_patent_app_number] => 11552944 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/552944
Integrated circuit testing module configured for set-up and hold time testing Oct 24, 2006 Issued
Array ( [id] => 366736 [patent_doc_number] => 07484151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-27 [patent_title] => 'Method and apparatus for testing logic circuit designs' [patent_app_type] => utility [patent_app_number] => 11/538245 [patent_app_country] => US [patent_app_date] => 2006-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 10824 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/484/07484151.pdf [firstpage_image] =>[orig_patent_app_number] => 11538245 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/538245
Method and apparatus for testing logic circuit designs Oct 2, 2006 Issued
Array ( [id] => 336817 [patent_doc_number] => 07509546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Test pattern compression for an integrated circuit test environment' [patent_app_type] => utility [patent_app_number] => 11/523111 [patent_app_country] => US [patent_app_date] => 2006-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7908 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/509/07509546.pdf [firstpage_image] =>[orig_patent_app_number] => 11523111 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/523111
Test pattern compression for an integrated circuit test environment Sep 17, 2006 Issued
Array ( [id] => 193021 [patent_doc_number] => 07644348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-05 [patent_title] => 'Method and apparatus for error detection and correction' [patent_app_type] => utility [patent_app_number] => 11/518824 [patent_app_country] => US [patent_app_date] => 2006-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8905 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/644/07644348.pdf [firstpage_image] =>[orig_patent_app_number] => 11518824 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/518824
Method and apparatus for error detection and correction Sep 10, 2006 Issued
Array ( [id] => 7589628 [patent_doc_number] => 07665005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-16 [patent_title] => 'In situ processor margin testing' [patent_app_type] => utility [patent_app_number] => 11/509856 [patent_app_country] => US [patent_app_date] => 2006-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4205 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/665/07665005.pdf [firstpage_image] =>[orig_patent_app_number] => 11509856 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/509856
In situ processor margin testing Aug 24, 2006 Issued
Array ( [id] => 4731727 [patent_doc_number] => 20080048705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Threshold voltage control apparatus, test apparatus, and circuit device' [patent_app_type] => utility [patent_app_number] => 11/509320 [patent_app_country] => US [patent_app_date] => 2006-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7176 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20080048705.pdf [firstpage_image] =>[orig_patent_app_number] => 11509320 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/509320
Threshold voltage control apparatus, test apparatus, and circuit device Aug 23, 2006 Issued
Array ( [id] => 4735592 [patent_doc_number] => 20080052574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Circuits and associated methods for improved debug and test of an application integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/508585 [patent_app_country] => US [patent_app_date] => 2006-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4087 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20080052574.pdf [firstpage_image] =>[orig_patent_app_number] => 11508585 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/508585
Circuits and associated methods for improved debug and test of an application integrated circuit Aug 22, 2006 Issued
Menu