Search

Christine Trinh Le Tu

Examiner (ID: 6386, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2133, 2117, 2111, 2313, 2784, 2785, 2138, 2413
Total Applications
1773
Issued Applications
1557
Pending Applications
64
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1536119 [patent_doc_number] => 06337257 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/499028 [patent_app_country] => US [patent_app_date] => 2000-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 8598 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/337/06337257.pdf [firstpage_image] =>[orig_patent_app_number] => 09499028 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/499028
Semiconductor device and method of manufacturing the same Feb 6, 2000 Issued
Array ( [id] => 4368394 [patent_doc_number] => 06287895 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Semiconductor package having enhanced ball grid array protective dummy members' [patent_app_type] => 1 [patent_app_number] => 9/493198 [patent_app_country] => US [patent_app_date] => 2000-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 3738 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287895.pdf [firstpage_image] =>[orig_patent_app_number] => 493198 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/493198
Semiconductor package having enhanced ball grid array protective dummy members Jan 27, 2000 Issued
Array ( [id] => 4301942 [patent_doc_number] => 06251736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Method for forming contactless MOS transistors and resulting devices, especially for use in non-volatile memory arrays' [patent_app_type] => 1 [patent_app_number] => 9/473368 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1977 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251736.pdf [firstpage_image] =>[orig_patent_app_number] => 473368 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/473368
Method for forming contactless MOS transistors and resulting devices, especially for use in non-volatile memory arrays Dec 27, 1999 Issued
Array ( [id] => 4321562 [patent_doc_number] => 06331450 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Method of manufacturing semiconductor device using group III nitride compound' [patent_app_type] => 1 [patent_app_number] => 9/468638 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 5023 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331450.pdf [firstpage_image] =>[orig_patent_app_number] => 468638 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/468638
Method of manufacturing semiconductor device using group III nitride compound Dec 21, 1999 Issued
Array ( [id] => 1561057 [patent_doc_number] => 06362033 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Self-aligned LDD formation with one-step implantation for transistor formation' [patent_app_type] => B1 [patent_app_number] => 09/460318 [patent_app_country] => US [patent_app_date] => 1999-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3159 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362033.pdf [firstpage_image] =>[orig_patent_app_number] => 09460318 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/460318
Self-aligned LDD formation with one-step implantation for transistor formation Dec 13, 1999 Issued
Array ( [id] => 4344368 [patent_doc_number] => 06284625 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method of forming a shallow groove isolation structure' [patent_app_type] => 1 [patent_app_number] => 9/434308 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4426 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284625.pdf [firstpage_image] =>[orig_patent_app_number] => 434308 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/434308
Method of forming a shallow groove isolation structure Nov 4, 1999 Issued
Array ( [id] => 4343303 [patent_doc_number] => 06284557 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Optical sensor by using tunneling diode' [patent_app_type] => 1 [patent_app_number] => 9/414928 [patent_app_country] => US [patent_app_date] => 1999-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2245 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284557.pdf [firstpage_image] =>[orig_patent_app_number] => 414928 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/414928
Optical sensor by using tunneling diode Oct 11, 1999 Issued
Array ( [id] => 4318623 [patent_doc_number] => 06248631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Method for forming a v-shaped floating gate' [patent_app_type] => 1 [patent_app_number] => 9/415788 [patent_app_country] => US [patent_app_date] => 1999-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 6293 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/248/06248631.pdf [firstpage_image] =>[orig_patent_app_number] => 415788 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/415788
Method for forming a v-shaped floating gate Oct 7, 1999 Issued
Array ( [id] => 4246674 [patent_doc_number] => 06136707 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Seed layers for interconnects and methods for fabricating such seed layers' [patent_app_type] => 1 [patent_app_number] => 9/410898 [patent_app_country] => US [patent_app_date] => 1999-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5075 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/136/06136707.pdf [firstpage_image] =>[orig_patent_app_number] => 410898 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/410898
Seed layers for interconnects and methods for fabricating such seed layers Oct 1, 1999 Issued
Array ( [id] => 4405871 [patent_doc_number] => 06232222 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Method of eliminating a critical mask using a blockout mask and a resulting semiconductor structure' [patent_app_type] => 1 [patent_app_number] => 9/395418 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2896 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232222.pdf [firstpage_image] =>[orig_patent_app_number] => 395418 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395418
Method of eliminating a critical mask using a blockout mask and a resulting semiconductor structure Sep 13, 1999 Issued
Array ( [id] => 1532722 [patent_doc_number] => 06410453 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Method of processing a substrate' [patent_app_type] => B1 [patent_app_number] => 09/391078 [patent_app_country] => US [patent_app_date] => 1999-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 3287 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/410/06410453.pdf [firstpage_image] =>[orig_patent_app_number] => 09391078 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/391078
Method of processing a substrate Sep 1, 1999 Issued
Array ( [id] => 5951490 [patent_doc_number] => 20020006713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-17 [patent_title] => 'OPTICAL ARTICLE, EXPOSURE APPARATUS OR OPTICAL SYSTEM USING IT, AND PROCESS FOR PRODUCING IT' [patent_app_type] => new [patent_app_number] => 09/386358 [patent_app_country] => US [patent_app_date] => 1999-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11220 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20020006713.pdf [firstpage_image] =>[orig_patent_app_number] => 09386358 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/386358
Optical article, exposure apparatus or optical system using it, and process for producing it Aug 30, 1999 Issued
Array ( [id] => 4275844 [patent_doc_number] => 06281110 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Method for making an integrated circuit including deutrium annealing of metal interconnect layers' [patent_app_type] => 1 [patent_app_number] => 9/361733 [patent_app_country] => US [patent_app_date] => 1999-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1613 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281110.pdf [firstpage_image] =>[orig_patent_app_number] => 361733 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/361733
Method for making an integrated circuit including deutrium annealing of metal interconnect layers Jul 26, 1999 Issued
Array ( [id] => 4269371 [patent_doc_number] => 06245595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Techniques for wafer level molding of underfill encapsulant' [patent_app_type] => 1 [patent_app_number] => 9/359074 [patent_app_country] => US [patent_app_date] => 1999-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4555 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/245/06245595.pdf [firstpage_image] =>[orig_patent_app_number] => 359074 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/359074
Techniques for wafer level molding of underfill encapsulant Jul 21, 1999 Issued
Array ( [id] => 4304268 [patent_doc_number] => 06326301 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Method for forming a dual inlaid copper interconnect structure' [patent_app_type] => 1 [patent_app_number] => 9/352134 [patent_app_country] => US [patent_app_date] => 1999-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 7716 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326301.pdf [firstpage_image] =>[orig_patent_app_number] => 352134 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/352134
Method for forming a dual inlaid copper interconnect structure Jul 12, 1999 Issued
Array ( [id] => 4301867 [patent_doc_number] => 06251731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Method for fabricating high-density and high-speed nand-type mask roms' [patent_app_type] => 1 [patent_app_number] => 9/351873 [patent_app_country] => US [patent_app_date] => 1999-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3193 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251731.pdf [firstpage_image] =>[orig_patent_app_number] => 351873 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/351873
Method for fabricating high-density and high-speed nand-type mask roms Jul 12, 1999 Issued
Array ( [id] => 4276313 [patent_doc_number] => 06281143 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Method of forming borderless contact' [patent_app_type] => 1 [patent_app_number] => 9/334864 [patent_app_country] => US [patent_app_date] => 1999-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1552 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281143.pdf [firstpage_image] =>[orig_patent_app_number] => 334864 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/334864
Method of forming borderless contact Jun 16, 1999 Issued
Array ( [id] => 4326406 [patent_doc_number] => 06319758 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Redundancy structure in self-aligned contact process' [patent_app_type] => 1 [patent_app_number] => 9/329783 [patent_app_country] => US [patent_app_date] => 1999-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 2665 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319758.pdf [firstpage_image] =>[orig_patent_app_number] => 329783 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/329783
Redundancy structure in self-aligned contact process Jun 9, 1999 Issued
Array ( [id] => 4321964 [patent_doc_number] => 06331476 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Thin film transistor and producing method thereof' [patent_app_type] => 1 [patent_app_number] => 9/316017 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14457 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331476.pdf [firstpage_image] =>[orig_patent_app_number] => 316017 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/316017
Thin film transistor and producing method thereof May 20, 1999 Issued
Array ( [id] => 4404605 [patent_doc_number] => 06271079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method of forming a trench capacitor' [patent_app_type] => 1 [patent_app_number] => 9/314154 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2448 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271079.pdf [firstpage_image] =>[orig_patent_app_number] => 314154 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314154
Method of forming a trench capacitor May 18, 1999 Issued
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