Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5137572 [patent_doc_number] => 20070079201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'Power-saving apparatus according to the operating mode of an embedded memory' [patent_app_type] => utility [patent_app_number] => 11/507581 [patent_app_country] => US [patent_app_date] => 2006-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3130 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20070079201.pdf [firstpage_image] =>[orig_patent_app_number] => 11507581 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/507581
Power-saving apparatus according to the operating mode of an embedded memory Aug 21, 2006 Abandoned
Array ( [id] => 4706417 [patent_doc_number] => 20080065941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'Meta-data driven test-data generation with controllable combinatorial coverage' [patent_app_type] => utility [patent_app_number] => 11/507416 [patent_app_country] => US [patent_app_date] => 2006-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9963 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20080065941.pdf [firstpage_image] =>[orig_patent_app_number] => 11507416 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/507416
Meta-data driven test-data generation with controllable combinatorial coverage Aug 20, 2006 Issued
Array ( [id] => 276099 [patent_doc_number] => 07562274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-14 [patent_title] => 'User data driven test control software application the requires no software maintenance' [patent_app_type] => utility [patent_app_number] => 11/465080 [patent_app_country] => US [patent_app_date] => 2006-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 10813 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/562/07562274.pdf [firstpage_image] =>[orig_patent_app_number] => 11465080 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/465080
User data driven test control software application the requires no software maintenance Aug 15, 2006 Issued
Array ( [id] => 4735594 [patent_doc_number] => 20080052576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Processor Fault Isolation' [patent_app_type] => utility [patent_app_number] => 11/464393 [patent_app_country] => US [patent_app_date] => 2006-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20080052576.pdf [firstpage_image] =>[orig_patent_app_number] => 11464393 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/464393
Processor fault isolation Aug 13, 2006 Issued
Array ( [id] => 297922 [patent_doc_number] => 07543201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-02 [patent_title] => 'Semiconductor devices including test circuits and related methods of testing' [patent_app_type] => utility [patent_app_number] => 11/463965 [patent_app_country] => US [patent_app_date] => 2006-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5049 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/543/07543201.pdf [firstpage_image] =>[orig_patent_app_number] => 11463965 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/463965
Semiconductor devices including test circuits and related methods of testing Aug 10, 2006 Issued
Array ( [id] => 4735597 [patent_doc_number] => 20080052579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'System and Method for Advanced Logic Built-in Self Test with Selection of Scan Channels' [patent_app_type] => utility [patent_app_number] => 11/463904 [patent_app_country] => US [patent_app_date] => 2006-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5019 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20080052579.pdf [firstpage_image] =>[orig_patent_app_number] => 11463904 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/463904
System and method for advanced logic built-in self test with selection of scan channels Aug 10, 2006 Issued
Array ( [id] => 309686 [patent_doc_number] => 07533314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Unit test extender' [patent_app_type] => utility [patent_app_number] => 11/463663 [patent_app_country] => US [patent_app_date] => 2006-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3671 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/533/07533314.pdf [firstpage_image] =>[orig_patent_app_number] => 11463663 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/463663
Unit test extender Aug 9, 2006 Issued
Array ( [id] => 265590 [patent_doc_number] => 07571364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-04 [patent_title] => 'Selectable JTAG or trace access with data store and output' [patent_app_type] => utility [patent_app_number] => 11/463479 [patent_app_country] => US [patent_app_date] => 2006-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 81 [patent_figures_cnt] => 114 [patent_no_of_words] => 41122 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/571/07571364.pdf [firstpage_image] =>[orig_patent_app_number] => 11463479 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/463479
Selectable JTAG or trace access with data store and output Aug 8, 2006 Issued
Array ( [id] => 5058726 [patent_doc_number] => 20070061648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'SHIFT REGISTER, SCANNING LINE DRIVING CIRCUIT, MATRIX TYPE DEVICE, ELECTRO-OPTIC DEVICE, AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 11/463115 [patent_app_country] => US [patent_app_date] => 2006-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4901 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20070061648.pdf [firstpage_image] =>[orig_patent_app_number] => 11463115 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/463115
Shift register, scanning line driving circuit, matrix type device, electro-optic device, and electronic device Aug 7, 2006 Issued
Array ( [id] => 829310 [patent_doc_number] => 07404123 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-22 [patent_title] => 'Automated test and characterization data analysis methods and arrangement' [patent_app_type] => utility [patent_app_number] => 11/462325 [patent_app_country] => US [patent_app_date] => 2006-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7200 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/404/07404123.pdf [firstpage_image] =>[orig_patent_app_number] => 11462325 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/462325
Automated test and characterization data analysis methods and arrangement Aug 2, 2006 Issued
Array ( [id] => 317047 [patent_doc_number] => 07526694 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-04-28 [patent_title] => 'Integrated circuit internal test circuit and method of testing therewith' [patent_app_type] => utility [patent_app_number] => 11/498368 [patent_app_country] => US [patent_app_date] => 2006-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6197 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/526/07526694.pdf [firstpage_image] =>[orig_patent_app_number] => 11498368 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/498368
Integrated circuit internal test circuit and method of testing therewith Aug 2, 2006 Issued
Array ( [id] => 598523 [patent_doc_number] => 07451369 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-11-11 [patent_title] => 'Scalable columnar boundary scan architecture for integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/498372 [patent_app_country] => US [patent_app_date] => 2006-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4601 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/451/07451369.pdf [firstpage_image] =>[orig_patent_app_number] => 11498372 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/498372
Scalable columnar boundary scan architecture for integrated circuits Aug 2, 2006 Issued
Array ( [id] => 302191 [patent_doc_number] => 07539923 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-05-26 [patent_title] => 'Circuit and method of transmitting a block of data' [patent_app_type] => utility [patent_app_number] => 11/498367 [patent_app_country] => US [patent_app_date] => 2006-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4802 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/539/07539923.pdf [firstpage_image] =>[orig_patent_app_number] => 11498367 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/498367
Circuit and method of transmitting a block of data Aug 2, 2006 Issued
Array ( [id] => 4735603 [patent_doc_number] => 20080052585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'Integrated testing apparatus, systems, and methods' [patent_app_type] => utility [patent_app_number] => 11/497849 [patent_app_country] => US [patent_app_date] => 2006-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4030 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20080052585.pdf [firstpage_image] =>[orig_patent_app_number] => 11497849 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/497849
Integrated testing apparatus, systems, and methods Aug 1, 2006 Issued
Array ( [id] => 4735599 [patent_doc_number] => 20080052581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'LOGIC BUILT-IN SELF-TEST CHANNEL SKIPPING DURING FUNCTIONAL SCAN OPERATIONS' [patent_app_type] => utility [patent_app_number] => 11/461806 [patent_app_country] => US [patent_app_date] => 2006-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1692 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20080052581.pdf [firstpage_image] =>[orig_patent_app_number] => 11461806 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/461806
Logic built-in self-test channel skipping during functional scan operations Aug 1, 2006 Issued
Array ( [id] => 336860 [patent_doc_number] => 07509551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Direct logic diagnostics with signature-based fault dictionaries' [patent_app_type] => utility [patent_app_number] => 11/497977 [patent_app_country] => US [patent_app_date] => 2006-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11294 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/509/07509551.pdf [firstpage_image] =>[orig_patent_app_number] => 11497977 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/497977
Direct logic diagnostics with signature-based fault dictionaries Jul 31, 2006 Issued
Array ( [id] => 355662 [patent_doc_number] => 07493543 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-02-17 [patent_title] => 'Determining timing associated with an input or output of an embedded circuit in an integrated circuit for testing' [patent_app_type] => utility [patent_app_number] => 11/490669 [patent_app_country] => US [patent_app_date] => 2006-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7017 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/493/07493543.pdf [firstpage_image] =>[orig_patent_app_number] => 11490669 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/490669
Determining timing associated with an input or output of an embedded circuit in an integrated circuit for testing Jul 19, 2006 Issued
Array ( [id] => 5660486 [patent_doc_number] => 20060251082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Time-Aware Best-Effort Hole-Filling Retry Method and System for Network Communications' [patent_app_type] => utility [patent_app_number] => 11/456524 [patent_app_country] => US [patent_app_date] => 2006-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7150 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20060251082.pdf [firstpage_image] =>[orig_patent_app_number] => 11456524 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/456524
Time-Aware Best-Effort Hole-Filling Retry Method and System for Network Communications Jul 9, 2006 Abandoned
Array ( [id] => 5928176 [patent_doc_number] => 20060242528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Error correction method for high density disc' [patent_app_type] => utility [patent_app_number] => 11/429307 [patent_app_country] => US [patent_app_date] => 2006-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3197 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20060242528.pdf [firstpage_image] =>[orig_patent_app_number] => 11429307 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/429307
Error correction method for high density disc May 7, 2006 Issued
Array ( [id] => 97456 [patent_doc_number] => 07739582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-15 [patent_title] => 'Error correction method for high density disc' [patent_app_type] => utility [patent_app_number] => 11/429340 [patent_app_country] => US [patent_app_date] => 2006-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 3206 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/739/07739582.pdf [firstpage_image] =>[orig_patent_app_number] => 11429340 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/429340
Error correction method for high density disc May 7, 2006 Issued
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