Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5238335 [patent_doc_number] => 20070130492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'Testable design methodology for clock domain crossing' [patent_app_type] => utility [patent_app_number] => 11/294761 [patent_app_country] => US [patent_app_date] => 2005-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3287 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20070130492.pdf [firstpage_image] =>[orig_patent_app_number] => 11294761 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/294761
Testable design methodology for clock domain crossing Dec 1, 2005 Issued
Array ( [id] => 5695922 [patent_doc_number] => 20060156069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'BDX data in stable states' [patent_app_type] => utility [patent_app_number] => 11/293067 [patent_app_country] => US [patent_app_date] => 2005-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 11965 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20060156069.pdf [firstpage_image] =>[orig_patent_app_number] => 11293067 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/293067
Adapter implemented background data transfers while tap in non-scan state Dec 1, 2005 Issued
Array ( [id] => 5079698 [patent_doc_number] => 20070122922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'Platform ASIC reliability' [patent_app_type] => utility [patent_app_number] => 11/287927 [patent_app_country] => US [patent_app_date] => 2005-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6131 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20070122922.pdf [firstpage_image] =>[orig_patent_app_number] => 11287927 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/287927
Platform ASIC reliability Nov 27, 2005 Issued
Array ( [id] => 423781 [patent_doc_number] => 07275196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-25 [patent_title] => 'Runtime reconfiguration of reconfigurable circuits' [patent_app_type] => utility [patent_app_number] => 11/285988 [patent_app_country] => US [patent_app_date] => 2005-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6040 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/275/07275196.pdf [firstpage_image] =>[orig_patent_app_number] => 11285988 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/285988
Runtime reconfiguration of reconfigurable circuits Nov 22, 2005 Issued
Array ( [id] => 188706 [patent_doc_number] => 07647544 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-01-12 [patent_title] => 'Disk drive implementing data path protection without writing the error detection code data to the disk' [patent_app_type] => utility [patent_app_number] => 11/284450 [patent_app_country] => US [patent_app_date] => 2005-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5182 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/647/07647544.pdf [firstpage_image] =>[orig_patent_app_number] => 11284450 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/284450
Disk drive implementing data path protection without writing the error detection code data to the disk Nov 21, 2005 Issued
Array ( [id] => 280017 [patent_doc_number] => 07558995 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-07-07 [patent_title] => 'Method and apparatus for eliminating noise induced errors during test of a programmable logic device' [patent_app_type] => utility [patent_app_number] => 11/285569 [patent_app_country] => US [patent_app_date] => 2005-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4365 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/558/07558995.pdf [firstpage_image] =>[orig_patent_app_number] => 11285569 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/285569
Method and apparatus for eliminating noise induced errors during test of a programmable logic device Nov 20, 2005 Issued
Array ( [id] => 5597886 [patent_doc_number] => 20060161804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-20 [patent_title] => 'Memory BISR controller architecture' [patent_app_type] => utility [patent_app_number] => 11/270077 [patent_app_country] => US [patent_app_date] => 2005-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20060161804.pdf [firstpage_image] =>[orig_patent_app_number] => 11270077 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/270077
Memory BISR controller architecture Nov 8, 2005 Issued
Array ( [id] => 5728632 [patent_doc_number] => 20060059393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-16 [patent_title] => 'Redundancy register architecture for soft-error tolerance and methods of making the same' [patent_app_type] => utility [patent_app_number] => 11/270411 [patent_app_country] => US [patent_app_date] => 2005-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3754 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20060059393.pdf [firstpage_image] =>[orig_patent_app_number] => 11270411 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/270411
Redundancy register architecture for soft-error tolerance and methods of making the same Nov 7, 2005 Issued
Array ( [id] => 4973159 [patent_doc_number] => 20070113162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Error code for wireless remote control device and method' [patent_app_type] => utility [patent_app_number] => 11/259813 [patent_app_country] => US [patent_app_date] => 2005-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8688 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20070113162.pdf [firstpage_image] =>[orig_patent_app_number] => 11259813 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/259813
Error code for wireless remote control device and method Oct 25, 2005 Abandoned
Array ( [id] => 5795105 [patent_doc_number] => 20060015786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'System and shadow bistable circuits coupled to output joining circuit' [patent_app_type] => utility [patent_app_number] => 11/218979 [patent_app_country] => US [patent_app_date] => 2005-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8037 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20060015786.pdf [firstpage_image] =>[orig_patent_app_number] => 11218979 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/218979
System and shadow bistable circuits coupled to output joining circuit Sep 1, 2005 Issued
Array ( [id] => 5847195 [patent_doc_number] => 20060123298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'PCI Express Physical Layer Built-In Self Test Architecture' [patent_app_type] => utility [patent_app_number] => 11/162153 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20060123298.pdf [firstpage_image] =>[orig_patent_app_number] => 11162153 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/162153
PCI express physical layer built-in self test architecture Aug 29, 2005 Issued
Array ( [id] => 5712006 [patent_doc_number] => 20060053352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Communications system, receiver, and method of estimating received signal quality' [patent_app_type] => utility [patent_app_number] => 11/210788 [patent_app_country] => US [patent_app_date] => 2005-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4940 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20060053352.pdf [firstpage_image] =>[orig_patent_app_number] => 11210788 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/210788
Communications system, receiver, and method of estimating received signal quality by using bit error rate Aug 24, 2005 Issued
Array ( [id] => 5108811 [patent_doc_number] => 20070067689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'In-circuit testing system and method' [patent_app_type] => utility [patent_app_number] => 11/210415 [patent_app_country] => US [patent_app_date] => 2005-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2507 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20070067689.pdf [firstpage_image] =>[orig_patent_app_number] => 11210415 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/210415
In-circuit testing system and method Aug 23, 2005 Issued
Array ( [id] => 317070 [patent_doc_number] => 07526704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-28 [patent_title] => 'Testing system and method allowing adjustment of signal transmit timing' [patent_app_type] => utility [patent_app_number] => 11/210406 [patent_app_country] => US [patent_app_date] => 2005-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6242 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/526/07526704.pdf [firstpage_image] =>[orig_patent_app_number] => 11210406 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/210406
Testing system and method allowing adjustment of signal transmit timing Aug 22, 2005 Issued
Array ( [id] => 5058722 [patent_doc_number] => 20070061644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Scan verification for a device under test' [patent_app_type] => utility [patent_app_number] => 11/206846 [patent_app_country] => US [patent_app_date] => 2005-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14061 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20070061644.pdf [firstpage_image] =>[orig_patent_app_number] => 11206846 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/206846
Scan verification for a scan-chain device under test Aug 17, 2005 Issued
Array ( [id] => 5058735 [patent_doc_number] => 20070061657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Delay fault testing apparatus' [patent_app_type] => utility [patent_app_number] => 11/203381 [patent_app_country] => US [patent_app_date] => 2005-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3871 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20070061657.pdf [firstpage_image] =>[orig_patent_app_number] => 11203381 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/203381
Delay fault testing apparatus Aug 11, 2005 Abandoned
Array ( [id] => 5916290 [patent_doc_number] => 20060237705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Method And Related Apparatus For Calibrating Signal Driving Parameters Between Chips' [patent_app_type] => utility [patent_app_number] => 11/161614 [patent_app_country] => US [patent_app_date] => 2005-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10702 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20060237705.pdf [firstpage_image] =>[orig_patent_app_number] => 11161614 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/161614
Method and related apparatus for calibrating signal driving parameters between chips Aug 9, 2005 Issued
Array ( [id] => 5190466 [patent_doc_number] => 20070168775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Programmable Memory Test Controller' [patent_app_type] => utility [patent_app_number] => 11/161437 [patent_app_country] => US [patent_app_date] => 2005-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3924 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20070168775.pdf [firstpage_image] =>[orig_patent_app_number] => 11161437 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/161437
Programmable Memory Test Controller Aug 2, 2005 Abandoned
Array ( [id] => 5893671 [patent_doc_number] => 20060002209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Mode entry circuit and method' [patent_app_type] => utility [patent_app_number] => 11/193258 [patent_app_country] => US [patent_app_date] => 2005-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3634 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20060002209.pdf [firstpage_image] =>[orig_patent_app_number] => 11193258 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/193258
Mode entry circuit and method Jul 28, 2005 Issued
Array ( [id] => 5847244 [patent_doc_number] => 20060123310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'System and method for modulation diversity' [patent_app_type] => utility [patent_app_number] => 11/192788 [patent_app_country] => US [patent_app_date] => 2005-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3975 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20060123310.pdf [firstpage_image] =>[orig_patent_app_number] => 11192788 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/192788
System and method for modulation diversity Jul 28, 2005 Issued
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