
Christine Trinh Le Tu
Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784 |
| Total Applications | 1748 |
| Issued Applications | 1571 |
| Pending Applications | 27 |
| Abandoned Applications | 152 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 333159
[patent_doc_number] => 07512857
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-03-31
[patent_title] => 'Pattern correction circuit'
[patent_app_type] => utility
[patent_app_number] => 11/193873
[patent_app_country] => US
[patent_app_date] => 2005-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4845
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/512/07512857.pdf
[firstpage_image] =>[orig_patent_app_number] => 11193873
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/193873 | Pattern correction circuit | Jul 28, 2005 | Issued |
Array
(
[id] => 5203688
[patent_doc_number] => 20070025167
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-01
[patent_title] => 'Method for testing a memory device, test unit for testing a memory device and memory device'
[patent_app_type] => utility
[patent_app_number] => 11/191146
[patent_app_country] => US
[patent_app_date] => 2005-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4554
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0025/20070025167.pdf
[firstpage_image] =>[orig_patent_app_number] => 11191146
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/191146 | Method for testing a memory device, test unit for testing a memory device and memory device | Jul 26, 2005 | Abandoned |
Array
(
[id] => 4780838
[patent_doc_number] => 20080288837
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-20
[patent_title] => 'Testing of a Circuit That has an Asynchronous Timing Circuit'
[patent_app_type] => utility
[patent_app_number] => 11/572930
[patent_app_country] => US
[patent_app_date] => 2005-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7231
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0288/20080288837.pdf
[firstpage_image] =>[orig_patent_app_number] => 11572930
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/572930 | Testing of a Circuit That has an Asynchronous Timing Circuit | Jul 20, 2005 | Abandoned |
Array
(
[id] => 5852980
[patent_doc_number] => 20060236171
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-10-19
[patent_title] => 'METHOD FOR DETECTING AND CORRECTING ERRORS OF ELECTRONIC APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 11/161022
[patent_app_country] => US
[patent_app_date] => 2005-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2595
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0236/20060236171.pdf
[firstpage_image] =>[orig_patent_app_number] => 11161022
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/161022 | METHOD FOR DETECTING AND CORRECTING ERRORS OF ELECTRONIC APPARATUS | Jul 19, 2005 | Abandoned |
Array
(
[id] => 478546
[patent_doc_number] => 07231565
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-12
[patent_title] => 'Method for performing built-in and at-speed test in system-on-chip'
[patent_app_type] => utility
[patent_app_number] => 11/160974
[patent_app_country] => US
[patent_app_date] => 2005-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1767
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/231/07231565.pdf
[firstpage_image] =>[orig_patent_app_number] => 11160974
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/160974 | Method for performing built-in and at-speed test in system-on-chip | Jul 17, 2005 | Issued |
Array
(
[id] => 4996286
[patent_doc_number] => 20070011631
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-11
[patent_title] => 'Harnessing machine learning to improve the success rate of stimuli generation'
[patent_app_type] => utility
[patent_app_number] => 11/177127
[patent_app_country] => US
[patent_app_date] => 2005-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6971
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0011/20070011631.pdf
[firstpage_image] =>[orig_patent_app_number] => 11177127
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/177127 | Harnessing machine learning to improve the success rate of stimuli generation | Jul 6, 2005 | Issued |
Array
(
[id] => 5243841
[patent_doc_number] => 20070022336
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-25
[patent_title] => 'Digital storage element with enable signal gating'
[patent_app_type] => utility
[patent_app_number] => 11/171528
[patent_app_country] => US
[patent_app_date] => 2005-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 11653
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0022/20070022336.pdf
[firstpage_image] =>[orig_patent_app_number] => 11171528
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/171528 | Digital storage element with enable signal gating | Jun 29, 2005 | Issued |
Array
(
[id] => 5243855
[patent_doc_number] => 20070022350
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-25
[patent_title] => 'Built-in waveform edge deskew using digital-locked loops and coincidence detectors in an automated test equipment system'
[patent_app_type] => utility
[patent_app_number] => 11/159790
[patent_app_country] => US
[patent_app_date] => 2005-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5643
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0022/20070022350.pdf
[firstpage_image] =>[orig_patent_app_number] => 11159790
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/159790 | Built-in waveform edge deskew using digital-locked loops and coincidence detectors in an automated test equipment system | Jun 22, 2005 | Issued |
Array
(
[id] => 549746
[patent_doc_number] => 07185240
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-27
[patent_title] => 'Apparatus and method for testing codec software by utilizing parallel processes'
[patent_app_type] => utility
[patent_app_number] => 11/157803
[patent_app_country] => US
[patent_app_date] => 2005-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5173
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/185/07185240.pdf
[firstpage_image] =>[orig_patent_app_number] => 11157803
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/157803 | Apparatus and method for testing codec software by utilizing parallel processes | Jun 21, 2005 | Issued |
Array
(
[id] => 5243838
[patent_doc_number] => 20070022333
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-25
[patent_title] => 'Testing of interconnects associated with memory cards'
[patent_app_type] => utility
[patent_app_number] => 11/155171
[patent_app_country] => US
[patent_app_date] => 2005-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4600
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0022/20070022333.pdf
[firstpage_image] =>[orig_patent_app_number] => 11155171
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/155171 | Testing of interconnects associated with memory cards | Jun 16, 2005 | Abandoned |
Array
(
[id] => 6979703
[patent_doc_number] => 20050289421
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-29
[patent_title] => 'Semiconductor chip'
[patent_app_type] => utility
[patent_app_number] => 11/152930
[patent_app_country] => US
[patent_app_date] => 2005-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 17859
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0289/20050289421.pdf
[firstpage_image] =>[orig_patent_app_number] => 11152930
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/152930 | Semiconductor chip | Jun 14, 2005 | Abandoned |
Array
(
[id] => 6979702
[patent_doc_number] => 20050289420
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-29
[patent_title] => 'Serial burn-in monitor'
[patent_app_type] => utility
[patent_app_number] => 11/151575
[patent_app_country] => US
[patent_app_date] => 2005-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1872
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0289/20050289420.pdf
[firstpage_image] =>[orig_patent_app_number] => 11151575
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/151575 | Serial burn-in monitor | Jun 12, 2005 | Issued |
Array
(
[id] => 343228
[patent_doc_number] => 07502979
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-10
[patent_title] => 'Pipelined scan structures for testing embedded cores'
[patent_app_type] => utility
[patent_app_number] => 11/150354
[patent_app_country] => US
[patent_app_date] => 2005-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 10422
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/502/07502979.pdf
[firstpage_image] =>[orig_patent_app_number] => 11150354
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/150354 | Pipelined scan structures for testing embedded cores | Jun 9, 2005 | Issued |
Array
(
[id] => 6930042
[patent_doc_number] => 20050281076
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-22
[patent_title] => 'Memory circuit comprising redundant memory areas'
[patent_app_type] => utility
[patent_app_number] => 11/145256
[patent_app_country] => US
[patent_app_date] => 2005-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3639
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0281/20050281076.pdf
[firstpage_image] =>[orig_patent_app_number] => 11145256
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/145256 | Memory circuit comprising redundant memory areas | Jun 2, 2005 | Issued |
Array
(
[id] => 486094
[patent_doc_number] => 07225381
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-05-29
[patent_title] => 'Error detection and correction method'
[patent_app_type] => utility
[patent_app_number] => 11/145047
[patent_app_country] => US
[patent_app_date] => 2005-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6272
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 21
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/225/07225381.pdf
[firstpage_image] =>[orig_patent_app_number] => 11145047
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/145047 | Error detection and correction method | Jun 1, 2005 | Issued |
Array
(
[id] => 5621250
[patent_doc_number] => 20060190785
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-24
[patent_title] => 'In-situ monitor of process and device parameters in integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 11/142758
[patent_app_country] => US
[patent_app_date] => 2005-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 11999
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0190/20060190785.pdf
[firstpage_image] =>[orig_patent_app_number] => 11142758
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/142758 | In-situ monitor of process and device parameters in integrated circuits | May 30, 2005 | Issued |
Array
(
[id] => 508737
[patent_doc_number] => 07210082
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-04-24
[patent_title] => 'Method for performing ATPG and fault simulation in a scan-based integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/140579
[patent_app_country] => US
[patent_app_date] => 2005-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7041
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/210/07210082.pdf
[firstpage_image] =>[orig_patent_app_number] => 11140579
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/140579 | Method for performing ATPG and fault simulation in a scan-based integrated circuit | May 30, 2005 | Issued |
Array
(
[id] => 605095
[patent_doc_number] => 07434139
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-07
[patent_title] => 'Remote module for a communications network'
[patent_app_type] => utility
[patent_app_number] => 11/140359
[patent_app_country] => US
[patent_app_date] => 2005-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8949
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/434/07434139.pdf
[firstpage_image] =>[orig_patent_app_number] => 11140359
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/140359 | Remote module for a communications network | May 25, 2005 | Issued |
Array
(
[id] => 5064921
[patent_doc_number] => 20070226563
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-27
[patent_title] => 'Test Method and Test Device for Testing an Integrated Circuit'
[patent_app_type] => utility
[patent_app_number] => 11/597139
[patent_app_country] => US
[patent_app_date] => 2005-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2460
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0226/20070226563.pdf
[firstpage_image] =>[orig_patent_app_number] => 11597139
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/597139 | Test Method and Test Device for Testing an Integrated Circuit | May 23, 2005 | Abandoned |
Array
(
[id] => 146728
[patent_doc_number] => 07689897
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-30
[patent_title] => 'Method and device for high speed testing of an integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/914700
[patent_app_country] => US
[patent_app_date] => 2005-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 4584
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/689/07689897.pdf
[firstpage_image] =>[orig_patent_app_number] => 11914700
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/914700 | Method and device for high speed testing of an integrated circuit | May 18, 2005 | Issued |