
Christine Trinh Le Tu
Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784 |
| Total Applications | 1748 |
| Issued Applications | 1571 |
| Pending Applications | 27 |
| Abandoned Applications | 152 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 599364
[patent_doc_number] => 07444556
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-28
[patent_title] => 'System and method of interleaving transmitted data'
[patent_app_type] => utility
[patent_app_number] => 11/128268
[patent_app_country] => US
[patent_app_date] => 2005-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 12385
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/444/07444556.pdf
[firstpage_image] =>[orig_patent_app_number] => 11128268
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/128268 | System and method of interleaving transmitted data | May 12, 2005 | Issued |
Array
(
[id] => 469639
[patent_doc_number] => 07240269
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-03
[patent_title] => 'Timing generator and semiconductor testing device'
[patent_app_type] => utility
[patent_app_number] => 11/126038
[patent_app_country] => US
[patent_app_date] => 2005-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 5011
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/240/07240269.pdf
[firstpage_image] =>[orig_patent_app_number] => 11126038
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/126038 | Timing generator and semiconductor testing device | May 9, 2005 | Issued |
Array
(
[id] => 513664
[patent_doc_number] => 07206980
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-17
[patent_title] => 'Integrated semiconductor memory'
[patent_app_type] => utility
[patent_app_number] => 11/123221
[patent_app_country] => US
[patent_app_date] => 2005-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5872
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/206/07206980.pdf
[firstpage_image] =>[orig_patent_app_number] => 11123221
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/123221 | Integrated semiconductor memory | May 5, 2005 | Issued |
Array
(
[id] => 7071218
[patent_doc_number] => 20050246603
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-03
[patent_title] => 'Pin coupler for an integrated circuit tester'
[patent_app_type] => utility
[patent_app_number] => 11/117968
[patent_app_country] => US
[patent_app_date] => 2005-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5008
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0246/20050246603.pdf
[firstpage_image] =>[orig_patent_app_number] => 11117968
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/117968 | Pin coupler for an integrated circuit tester | Apr 28, 2005 | Issued |
Array
(
[id] => 5836586
[patent_doc_number] => 20060248418
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-02
[patent_title] => 'Scan test expansion module'
[patent_app_type] => utility
[patent_app_number] => 11/116616
[patent_app_country] => US
[patent_app_date] => 2005-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2322
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0248/20060248418.pdf
[firstpage_image] =>[orig_patent_app_number] => 11116616
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/116616 | Scan test expansion module | Apr 27, 2005 | Issued |
Array
(
[id] => 7178233
[patent_doc_number] => 20050204240
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-15
[patent_title] => 'Test data generating system and method to test high-speed actual operation'
[patent_app_type] => utility
[patent_app_number] => 11/108816
[patent_app_country] => US
[patent_app_date] => 2005-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 9615
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 26
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0204/20050204240.pdf
[firstpage_image] =>[orig_patent_app_number] => 11108816
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/108816 | Test data generating system and method to test high-speed actual operation | Apr 18, 2005 | Abandoned |
Array
(
[id] => 481606
[patent_doc_number] => 07228471
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-05
[patent_title] => 'System and method for testing a data storage device without revealing memory content'
[patent_app_type] => utility
[patent_app_number] => 11/098496
[patent_app_country] => US
[patent_app_date] => 2005-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 3372
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/228/07228471.pdf
[firstpage_image] =>[orig_patent_app_number] => 11098496
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/098496 | System and method for testing a data storage device without revealing memory content | Apr 4, 2005 | Issued |
Array
(
[id] => 832676
[patent_doc_number] => 07401275
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-07-15
[patent_title] => 'Automated test and characterization web services'
[patent_app_type] => utility
[patent_app_number] => 11/093094
[patent_app_country] => US
[patent_app_date] => 2005-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5891
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/401/07401275.pdf
[firstpage_image] =>[orig_patent_app_number] => 11093094
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/093094 | Automated test and characterization web services | Mar 27, 2005 | Issued |
Array
(
[id] => 5698889
[patent_doc_number] => 20060215573
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-28
[patent_title] => 'Systems and methods for identifying system links'
[patent_app_type] => utility
[patent_app_number] => 11/088648
[patent_app_country] => US
[patent_app_date] => 2005-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3606
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0215/20060215573.pdf
[firstpage_image] =>[orig_patent_app_number] => 11088648
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/088648 | Systems and methods for identifying system links | Mar 23, 2005 | Issued |
Array
(
[id] => 823522
[patent_doc_number] => 07409609
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-08-05
[patent_title] => 'Integrated circuit with a control input that can be disabled'
[patent_app_type] => utility
[patent_app_number] => 11/079889
[patent_app_country] => US
[patent_app_date] => 2005-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 5809
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/409/07409609.pdf
[firstpage_image] =>[orig_patent_app_number] => 11079889
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/079889 | Integrated circuit with a control input that can be disabled | Mar 13, 2005 | Issued |
Array
(
[id] => 7228721
[patent_doc_number] => 20050261790
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-24
[patent_title] => 'Method and apparatus to correct erroneous audio data and a digital audio signal processing system employing the same'
[patent_app_type] => utility
[patent_app_number] => 11/072619
[patent_app_country] => US
[patent_app_date] => 2005-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4035
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0261/20050261790.pdf
[firstpage_image] =>[orig_patent_app_number] => 11072619
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/072619 | Method and apparatus to correct erroneous audio data and a digital audio signal processing system employing the same | Mar 6, 2005 | Abandoned |
Array
(
[id] => 7049611
[patent_doc_number] => 20050185498
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-25
[patent_title] => 'Timing calibration pattern for SLDRAM'
[patent_app_type] => utility
[patent_app_number] => 11/059645
[patent_app_country] => US
[patent_app_date] => 2005-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4303
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0185/20050185498.pdf
[firstpage_image] =>[orig_patent_app_number] => 11059645
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/059645 | Timing calibration pattern for SLDRAM | Feb 16, 2005 | Abandoned |
Array
(
[id] => 7073643
[patent_doc_number] => 20050146910
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-07
[patent_title] => 'Method and apparatus for reconfigurable memory'
[patent_app_type] => utility
[patent_app_number] => 11/040954
[patent_app_country] => US
[patent_app_date] => 2005-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7920
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0146/20050146910.pdf
[firstpage_image] =>[orig_patent_app_number] => 11040954
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/040954 | Method and apparatus for reconfigurable memory | Jan 20, 2005 | Issued |
Array
(
[id] => 5597906
[patent_doc_number] => 20060161824
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-20
[patent_title] => 'System and method of testing a plurality of memory blocks of an integrated circuit in parallel'
[patent_app_type] => utility
[patent_app_number] => 11/039666
[patent_app_country] => US
[patent_app_date] => 2005-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2893
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0161/20060161824.pdf
[firstpage_image] =>[orig_patent_app_number] => 11039666
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/039666 | System and method of testing a plurality of memory blocks of an integrated circuit in parallel | Jan 19, 2005 | Issued |
Array
(
[id] => 5597908
[patent_doc_number] => 20060161826
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-20
[patent_title] => 'Method and system of modifying data in functional latches of a logic unit during scan chain testing thereof'
[patent_app_type] => utility
[patent_app_number] => 11/038733
[patent_app_country] => US
[patent_app_date] => 2005-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3403
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0161/20060161826.pdf
[firstpage_image] =>[orig_patent_app_number] => 11038733
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/038733 | Method and system of modifying data in functional latches of a logic unit during scan chain testing thereof | Jan 19, 2005 | Issued |
Array
(
[id] => 796915
[patent_doc_number] => 07430694
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-30
[patent_title] => 'Memory BISR architecture for a slice'
[patent_app_type] => utility
[patent_app_number] => 11/038698
[patent_app_country] => US
[patent_app_date] => 2005-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 4761
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/430/07430694.pdf
[firstpage_image] =>[orig_patent_app_number] => 11038698
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/038698 | Memory BISR architecture for a slice | Jan 19, 2005 | Issued |
Array
(
[id] => 5597911
[patent_doc_number] => 20060161829
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-20
[patent_title] => 'Test apparatus and test method'
[patent_app_type] => utility
[patent_app_number] => 11/039394
[patent_app_country] => US
[patent_app_date] => 2005-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8239
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0161/20060161829.pdf
[firstpage_image] =>[orig_patent_app_number] => 11039394
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/039394 | Test apparatus and test method | Jan 18, 2005 | Issued |
Array
(
[id] => 5597915
[patent_doc_number] => 20060161833
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-20
[patent_title] => 'Software testing'
[patent_app_type] => utility
[patent_app_number] => 11/037597
[patent_app_country] => US
[patent_app_date] => 2005-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4783
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0161/20060161833.pdf
[firstpage_image] =>[orig_patent_app_number] => 11037597
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/037597 | Software testing | Jan 17, 2005 | Issued |
Array
(
[id] => 569522
[patent_doc_number] => 07171611
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-30
[patent_title] => 'Apparatus for determining the access time and/or the minimally allowable cycle time of a memory'
[patent_app_type] => utility
[patent_app_number] => 11/036542
[patent_app_country] => US
[patent_app_date] => 2005-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 5021
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/171/07171611.pdf
[firstpage_image] =>[orig_patent_app_number] => 11036542
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/036542 | Apparatus for determining the access time and/or the minimally allowable cycle time of a memory | Jan 13, 2005 | Issued |
Array
(
[id] => 447467
[patent_doc_number] => 07257750
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-08-14
[patent_title] => 'Self-verification of configuration memory in programmable logic devices'
[patent_app_type] => utility
[patent_app_number] => 11/036630
[patent_app_country] => US
[patent_app_date] => 2005-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3597
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/257/07257750.pdf
[firstpage_image] =>[orig_patent_app_number] => 11036630
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/036630 | Self-verification of configuration memory in programmable logic devices | Jan 12, 2005 | Issued |