Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 451325 [patent_doc_number] => 07254758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-07 [patent_title] => 'Method and apparatus for testing circuit units to be tested with different test mode data sets' [patent_app_type] => utility [patent_app_number] => 11/034236 [patent_app_country] => US [patent_app_date] => 2005-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2826 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/254/07254758.pdf [firstpage_image] =>[orig_patent_app_number] => 11034236 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/034236
Method and apparatus for testing circuit units to be tested with different test mode data sets Jan 11, 2005 Issued
Array ( [id] => 481608 [patent_doc_number] => 07228472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-05 [patent_title] => 'System and method to control data capture' [patent_app_type] => utility [patent_app_number] => 11/032928 [patent_app_country] => US [patent_app_date] => 2005-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10705 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/228/07228472.pdf [firstpage_image] =>[orig_patent_app_number] => 11032928 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/032928
System and method to control data capture Jan 10, 2005 Issued
Array ( [id] => 7006877 [patent_doc_number] => 20050172190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Method and apparatus for accessing hidden data in a boundary scan test interface' [patent_app_type] => utility [patent_app_number] => 11/032006 [patent_app_country] => US [patent_app_date] => 2005-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2530 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20050172190.pdf [firstpage_image] =>[orig_patent_app_number] => 11032006 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/032006
Method and apparatus for accessing hidden data in a boundary scan test interface Jan 10, 2005 Issued
Array ( [id] => 7038131 [patent_doc_number] => 20050157565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Semiconductor device for detecting memory failure and method thereof' [patent_app_type] => utility [patent_app_number] => 11/032112 [patent_app_country] => US [patent_app_date] => 2005-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4680 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20050157565.pdf [firstpage_image] =>[orig_patent_app_number] => 11032112 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/032112
Semiconductor device for detecting memory failure and method thereof Jan 10, 2005 Abandoned
Array ( [id] => 7006878 [patent_doc_number] => 20050172191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Method and apparatus for transferring hidden signals in a boundary scan test interface' [patent_app_type] => utility [patent_app_number] => 11/032008 [patent_app_country] => US [patent_app_date] => 2005-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1955 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20050172191.pdf [firstpage_image] =>[orig_patent_app_number] => 11032008 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/032008
Method and apparatus for transferring hidden signals in a boundary scan test interface Jan 10, 2005 Issued
Array ( [id] => 4780840 [patent_doc_number] => 20080288839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'Jtag Test Architecture For Multi-Chip Pack' [patent_app_type] => utility [patent_app_number] => 10/585607 [patent_app_country] => US [patent_app_date] => 2005-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1677 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20080288839.pdf [firstpage_image] =>[orig_patent_app_number] => 10585607 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/585607
JTAG test architecture for multi-chip pack Jan 4, 2005 Issued
Array ( [id] => 519088 [patent_doc_number] => 07203877 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-10 [patent_title] => 'Failure analysis and testing of semi-conductor devices using intelligent software on automated test equipment (ATE)' [patent_app_type] => utility [patent_app_number] => 11/028695 [patent_app_country] => US [patent_app_date] => 2005-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 20798 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/203/07203877.pdf [firstpage_image] =>[orig_patent_app_number] => 11028695 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/028695
Failure analysis and testing of semi-conductor devices using intelligent software on automated test equipment (ATE) Jan 3, 2005 Issued
Array ( [id] => 6962635 [patent_doc_number] => 20050216811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Apparatus for testing USB memory and method thereof' [patent_app_type] => utility [patent_app_number] => 11/027957 [patent_app_country] => US [patent_app_date] => 2005-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3155 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20050216811.pdf [firstpage_image] =>[orig_patent_app_number] => 11027957 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/027957
Apparatus for testing USB memory and method thereof Jan 3, 2005 Issued
Array ( [id] => 374995 [patent_doc_number] => 07475303 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-01-06 [patent_title] => 'HyperJTAG system including debug probe, on-chip instrumentation, and protocol' [patent_app_type] => utility [patent_app_number] => 11/026324 [patent_app_country] => US [patent_app_date] => 2004-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8385 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/475/07475303.pdf [firstpage_image] =>[orig_patent_app_number] => 11026324 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/026324
HyperJTAG system including debug probe, on-chip instrumentation, and protocol Dec 28, 2004 Issued
Array ( [id] => 478527 [patent_doc_number] => 07231560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-12 [patent_title] => 'Apparatus and method for testing motherboard having PCI express devices' [patent_app_type] => utility [patent_app_number] => 10/985461 [patent_app_country] => US [patent_app_date] => 2004-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3121 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/231/07231560.pdf [firstpage_image] =>[orig_patent_app_number] => 10985461 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/985461
Apparatus and method for testing motherboard having PCI express devices Nov 9, 2004 Issued
Array ( [id] => 7013721 [patent_doc_number] => 20050066247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Full-speed BIST controller for testing embedded synchronous memories' [patent_app_type] => utility [patent_app_number] => 10/985539 [patent_app_country] => US [patent_app_date] => 2004-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5724 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20050066247.pdf [firstpage_image] =>[orig_patent_app_number] => 10985539 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/985539
Full-speed BIST controller for testing embedded synchronous memories Nov 8, 2004 Issued
Array ( [id] => 469634 [patent_doc_number] => 07240267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-03 [patent_title] => 'System and method for conducting BIST operations' [patent_app_type] => utility [patent_app_number] => 10/983944 [patent_app_country] => US [patent_app_date] => 2004-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2069 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/240/07240267.pdf [firstpage_image] =>[orig_patent_app_number] => 10983944 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/983944
System and method for conducting BIST operations Nov 7, 2004 Issued
Array ( [id] => 7193859 [patent_doc_number] => 20050193300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-01 [patent_title] => 'Semiconductor integrated circuit detecting glitch noise and test method of the same' [patent_app_type] => utility [patent_app_number] => 10/982676 [patent_app_country] => US [patent_app_date] => 2004-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8242 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20050193300.pdf [firstpage_image] =>[orig_patent_app_number] => 10982676 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/982676
Semiconductor integrated circuit detecting glitch noise and test method of the same Nov 4, 2004 Issued
Array ( [id] => 7601883 [patent_doc_number] => 07237163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-26 [patent_title] => 'Leakage current reduction system and method' [patent_app_type] => utility [patent_app_number] => 10/982111 [patent_app_country] => US [patent_app_date] => 2004-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3612 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/237/07237163.pdf [firstpage_image] =>[orig_patent_app_number] => 10982111 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/982111
Leakage current reduction system and method Nov 4, 2004 Issued
Array ( [id] => 7042622 [patent_doc_number] => 20050160336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Semiconductor LSI circuit with scan circuit, scan circuit system, scanning test system and method' [patent_app_type] => utility [patent_app_number] => 10/981986 [patent_app_country] => US [patent_app_date] => 2004-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 8772 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20050160336.pdf [firstpage_image] =>[orig_patent_app_number] => 10981986 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/981986
Semiconductor LSI circuit with scan circuit, scan circuit system, scanning test system and method Nov 4, 2004 Issued
Array ( [id] => 481617 [patent_doc_number] => 07228476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-05 [patent_title] => 'System and method for testing integrated circuits at operational speed using high-frequency clock converter' [patent_app_type] => utility [patent_app_number] => 10/982275 [patent_app_country] => US [patent_app_date] => 2004-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4971 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/228/07228476.pdf [firstpage_image] =>[orig_patent_app_number] => 10982275 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/982275
System and method for testing integrated circuits at operational speed using high-frequency clock converter Nov 4, 2004 Issued
Array ( [id] => 5778509 [patent_doc_number] => 20060107149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/980938 [patent_app_country] => US [patent_app_date] => 2004-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9135 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20060107149.pdf [firstpage_image] =>[orig_patent_app_number] => 10980938 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/980938
Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit Nov 3, 2004 Issued
Array ( [id] => 5809464 [patent_doc_number] => 20060095820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Method, system, and program product for boundary I/O testing employing a logic built-in self-test of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/981225 [patent_app_country] => US [patent_app_date] => 2004-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9106 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095820.pdf [firstpage_image] =>[orig_patent_app_number] => 10981225 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/981225
Method, system, and program product for boundary I/O testing employing a logic built-in self-test of an integrated circuit Nov 3, 2004 Issued
Array ( [id] => 5809462 [patent_doc_number] => 20060095818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'System and method for automatic masking of compressed scan chains with unbalanced lengths' [patent_app_type] => utility [patent_app_number] => 10/980961 [patent_app_country] => US [patent_app_date] => 2004-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10647 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095818.pdf [firstpage_image] =>[orig_patent_app_number] => 10980961 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/980961
System and method for automatic masking of compressed scan chains with unbalanced lengths Nov 3, 2004 Issued
Array ( [id] => 7112890 [patent_doc_number] => 20050210346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Closed loop dynamic power management' [patent_app_type] => utility [patent_app_number] => 10/978950 [patent_app_country] => US [patent_app_date] => 2004-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2126 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20050210346.pdf [firstpage_image] =>[orig_patent_app_number] => 10978950 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/978950
Closed loop dynamic power management Oct 31, 2004 Abandoned
Menu