Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5809466 [patent_doc_number] => 20060095822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Generation of test vectors for testing electronic circuits taking into account of defect probability' [patent_app_type] => utility [patent_app_number] => 10/979582 [patent_app_country] => US [patent_app_date] => 2004-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3183 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095822.pdf [firstpage_image] =>[orig_patent_app_number] => 10979582 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/979582
Generation of test vectors for testing electronic circuits taking into account of defect probability Oct 31, 2004 Abandoned
Array ( [id] => 860485 [patent_doc_number] => 07376872 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-20 [patent_title] => 'Testing embedded memory in integrated circuits such as programmable logic devices' [patent_app_type] => utility [patent_app_number] => 10/978899 [patent_app_country] => US [patent_app_date] => 2004-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3469 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/376/07376872.pdf [firstpage_image] =>[orig_patent_app_number] => 10978899 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/978899
Testing embedded memory in integrated circuits such as programmable logic devices Oct 31, 2004 Issued
Array ( [id] => 478553 [patent_doc_number] => 07231568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-12 [patent_title] => 'System debugging device and system debugging method' [patent_app_type] => utility [patent_app_number] => 10/975397 [patent_app_country] => US [patent_app_date] => 2004-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3346 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/231/07231568.pdf [firstpage_image] =>[orig_patent_app_number] => 10975397 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/975397
System debugging device and system debugging method Oct 28, 2004 Issued
Array ( [id] => 374998 [patent_doc_number] => 07475306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-06 [patent_title] => 'Scan test method, integrated circuit, and scan test circuit' [patent_app_type] => utility [patent_app_number] => 10/974741 [patent_app_country] => US [patent_app_date] => 2004-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5365 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/475/07475306.pdf [firstpage_image] =>[orig_patent_app_number] => 10974741 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/974741
Scan test method, integrated circuit, and scan test circuit Oct 27, 2004 Issued
Array ( [id] => 5744379 [patent_doc_number] => 20060090105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-27 [patent_title] => 'Built-in self test for read-only memory including a diagnostic mode' [patent_app_type] => utility [patent_app_number] => 10/974084 [patent_app_country] => US [patent_app_date] => 2004-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2205 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20060090105.pdf [firstpage_image] =>[orig_patent_app_number] => 10974084 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/974084
Built-in self test for read-only memory including a diagnostic mode Oct 26, 2004 Abandoned
Array ( [id] => 5744380 [patent_doc_number] => 20060090106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-27 [patent_title] => 'Generalized BIST for multiport memories' [patent_app_type] => utility [patent_app_number] => 10/974450 [patent_app_country] => US [patent_app_date] => 2004-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7008 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20060090106.pdf [firstpage_image] =>[orig_patent_app_number] => 10974450 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/974450
Generalized BIST for multiport memories Oct 26, 2004 Abandoned
Array ( [id] => 241433 [patent_doc_number] => 07594159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-22 [patent_title] => 'Signature field in a latency measurement frame' [patent_app_type] => utility [patent_app_number] => 10/974214 [patent_app_country] => US [patent_app_date] => 2004-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 9435 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/594/07594159.pdf [firstpage_image] =>[orig_patent_app_number] => 10974214 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/974214
Signature field in a latency measurement frame Oct 25, 2004 Issued
Array ( [id] => 6974022 [patent_doc_number] => 20050039098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-17 [patent_title] => 'Apparatus and method for self testing programmable logic arrays' [patent_app_type] => utility [patent_app_number] => 10/947811 [patent_app_country] => US [patent_app_date] => 2004-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 11151 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20050039098.pdf [firstpage_image] =>[orig_patent_app_number] => 10947811 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/947811
Apparatus and method for self testing programmable logic arrays Sep 21, 2004 Abandoned
Array ( [id] => 5182102 [patent_doc_number] => 20070053445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-08 [patent_title] => 'System and method for providing video content and concealment dependent error protection and scheduling algorithms' [patent_app_type] => utility [patent_app_number] => 10/573081 [patent_app_country] => US [patent_app_date] => 2004-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3899 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20070053445.pdf [firstpage_image] =>[orig_patent_app_number] => 10573081 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/573081
System and method for providing video content and concealment dependent error protection and scheduling algorithms Sep 20, 2004 Abandoned
Array ( [id] => 5728625 [patent_doc_number] => 20060059386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-16 [patent_title] => 'Testing embedded memory in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/929199 [patent_app_country] => US [patent_app_date] => 2004-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3721 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20060059386.pdf [firstpage_image] =>[orig_patent_app_number] => 10929199 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/929199
Testing embedded memory in an integrated circuit Aug 29, 2004 Issued
Array ( [id] => 7359474 [patent_doc_number] => 20040250199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Error correction method for high density disc' [patent_app_type] => new [patent_app_number] => 10/890226 [patent_app_country] => US [patent_app_date] => 2004-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3194 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20040250199.pdf [firstpage_image] =>[orig_patent_app_number] => 10890226 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/890226
Error correction method for high density disc Jul 13, 2004 Issued
Array ( [id] => 7359473 [patent_doc_number] => 20040250198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Error correction method for high density disc' [patent_app_type] => new [patent_app_number] => 10/890225 [patent_app_country] => US [patent_app_date] => 2004-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3189 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20040250198.pdf [firstpage_image] =>[orig_patent_app_number] => 10890225 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/890225
Error correction method for high density disc Jul 13, 2004 Issued
Array ( [id] => 5896553 [patent_doc_number] => 20060005092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Cache based physical layer self test' [patent_app_type] => utility [patent_app_number] => 10/882966 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3707 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20060005092.pdf [firstpage_image] =>[orig_patent_app_number] => 10882966 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/882966
Cache based physical layer self test Jun 29, 2004 Issued
Array ( [id] => 540215 [patent_doc_number] => 07188284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Error detecting circuit' [patent_app_type] => utility [patent_app_number] => 10/882523 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7484 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/188/07188284.pdf [firstpage_image] =>[orig_patent_app_number] => 10882523 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/882523
Error detecting circuit Jun 29, 2004 Issued
Array ( [id] => 469578 [patent_doc_number] => 07240252 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-07-03 [patent_title] => 'Pulse interference testing in a CDMA communication system' [patent_app_type] => utility [patent_app_number] => 10/883251 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3903 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/240/07240252.pdf [firstpage_image] =>[orig_patent_app_number] => 10883251 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/883251
Pulse interference testing in a CDMA communication system Jun 29, 2004 Issued
Array ( [id] => 626495 [patent_doc_number] => 07139951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-21 [patent_title] => 'Scan enabled storage device' [patent_app_type] => utility [patent_app_number] => 10/880354 [patent_app_country] => US [patent_app_date] => 2004-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4363 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/139/07139951.pdf [firstpage_image] =>[orig_patent_app_number] => 10880354 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/880354
Scan enabled storage device Jun 28, 2004 Issued
Array ( [id] => 519128 [patent_doc_number] => 07203881 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-04-10 [patent_title] => 'System and method for simulating system operation' [patent_app_type] => utility [patent_app_number] => 10/880031 [patent_app_country] => US [patent_app_date] => 2004-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 45 [patent_no_of_words] => 60648 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/203/07203881.pdf [firstpage_image] =>[orig_patent_app_number] => 10880031 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/880031
System and method for simulating system operation Jun 28, 2004 Issued
Array ( [id] => 513645 [patent_doc_number] => 07206979 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-04-17 [patent_title] => 'Method and apparatus for at-speed diagnostics of embedded memories' [patent_app_type] => utility [patent_app_number] => 10/878817 [patent_app_country] => US [patent_app_date] => 2004-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7055 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/206/07206979.pdf [firstpage_image] =>[orig_patent_app_number] => 10878817 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/878817
Method and apparatus for at-speed diagnostics of embedded memories Jun 27, 2004 Issued
Array ( [id] => 7321589 [patent_doc_number] => 20040225937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'Testing of integrated circuit devices' [patent_app_type] => new [patent_app_number] => 10/870365 [patent_app_country] => US [patent_app_date] => 2004-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6860 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20040225937.pdf [firstpage_image] =>[orig_patent_app_number] => 10870365 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/870365
Testing of integrated circuit devices Jun 16, 2004 Issued
Array ( [id] => 226973 [patent_doc_number] => 07607054 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-20 [patent_title] => 'Method of improving the interface efficiency in a communications network' [patent_app_type] => utility [patent_app_number] => 10/863233 [patent_app_country] => US [patent_app_date] => 2004-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3313 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/607/07607054.pdf [firstpage_image] =>[orig_patent_app_number] => 10863233 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/863233
Method of improving the interface efficiency in a communications network Jun 8, 2004 Issued
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