Christine Trinh Le Tu

Array ( [id] => 7359541 [patent_doc_number] => 20040250207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Apparatus and method for providing near-optimal representations over redundant dictionaries' [patent_app_type] => new [patent_app_number] => 10/851586 [patent_app_country] => US [patent_app_date] => 2004-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 11128 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20040250207.pdf [firstpage_image] =>[orig_patent_app_number] => 10851586 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 860487 [patent_doc_number] => 07376874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-20 [patent_title] => 'Method of controlling a test mode of a circuit' [patent_app_type] => utility [patent_app_number] => 10/804371 [patent_app_country] => US [patent_app_date] => 2004-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2517 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/376/07376874.pdf [firstpage_image] =>[orig_patent_app_number] => 10804371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7178165 [patent_doc_number] => 20050204216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-15 [patent_title] => 'Method and apparatus for customizing and monitoring multiple interfaces and implementing enhanced fault tolerance and isolation features' [patent_app_type] => utility [patent_app_number] => 10/798912 [patent_app_country] => US [patent_app_date] => 2004-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2162 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20050204216.pdf [firstpage_image] =>[orig_patent_app_number] => 10798912 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 494110 [patent_doc_number] => 07219278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Configurator arrangement and approach therefor' [patent_app_type] => utility [patent_app_number] => 10/796484 [patent_app_country] => US [patent_app_date] => 2004-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7076 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/219/07219278.pdf [firstpage_image] =>[orig_patent_app_number] => 10796484 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7353829 [patent_doc_number] => 20040193979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-30 [patent_title] => 'Circuit configurator arrangement and approach therefor' [patent_app_type] => new [patent_app_number] => 10/796480 [patent_app_country] => US [patent_app_date] => 2004-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7427 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20040193979.pdf [firstpage_image] =>[orig_patent_app_number] => 10796480 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 619860 [patent_doc_number] => 07146550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-05 [patent_title] => 'Isolation testing circuit and testing circuit optimization method' [patent_app_type] => utility [patent_app_number] => 10/792809 [patent_app_country] => US [patent_app_date] => 2004-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4417 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/146/07146550.pdf [firstpage_image] =>[orig_patent_app_number] => 10792809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 555039 [patent_doc_number] => 07181663 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Wireless no-touch testing of integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/790906 [patent_app_country] => US [patent_app_date] => 2004-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4840 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/181/07181663.pdf [firstpage_image] =>[orig_patent_app_number] => 10790906 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7193857 [patent_doc_number] => 20050193299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-01 [patent_title] => 'Method and/or apparatus for performing static timing analysis on a chip in scan mode with multiple scan clocks' [patent_app_type] => utility [patent_app_number] => 10/789883 [patent_app_country] => US [patent_app_date] => 2004-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3066 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20050193299.pdf [firstpage_image] =>[orig_patent_app_number] => 10789883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 555032 [patent_doc_number] => 07181662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'On-chip test apparatus' [patent_app_type] => utility [patent_app_number] => 10/789300 [patent_app_country] => US [patent_app_date] => 2004-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2940 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/181/07181662.pdf [firstpage_image] =>[orig_patent_app_number] => 10789300 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 431474 [patent_doc_number] => 07269772 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-11 [patent_title] => 'Method and apparatus for built-in self-test (BIST) of integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/785826 [patent_app_country] => US [patent_app_date] => 2004-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6192 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/269/07269772.pdf [firstpage_image] =>[orig_patent_app_number] => 10785826 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7052571 [patent_doc_number] => 20050188290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'Method and structure for picosecond-imaging-circuit-analysis based built-in-self-test diagnostic' [patent_app_type] => utility [patent_app_number] => 10/780878 [patent_app_country] => US [patent_app_date] => 2004-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6335 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20050188290.pdf [firstpage_image] =>[orig_patent_app_number] => 10780878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 706958 [patent_doc_number] => 07065693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Implementation of test patterns in automated test equipment' [patent_app_type] => utility [patent_app_number] => 10/778753 [patent_app_country] => US [patent_app_date] => 2004-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2365 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/065/07065693.pdf [firstpage_image] =>[orig_patent_app_number] => 10778753 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 649122 [patent_doc_number] => 07120840 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-10 [patent_title] => 'Method and system for improved ATE timing calibration at a device under test' [patent_app_type] => utility [patent_app_number] => 10/773698 [patent_app_country] => US [patent_app_date] => 2004-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 7224 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/120/07120840.pdf [firstpage_image] =>[orig_patent_app_number] => 10773698 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 659560 [patent_doc_number] => 07111227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-19 [patent_title] => 'Methods and systems of using result buffers in parity operations' [patent_app_type] => utility [patent_app_number] => 10/728274 [patent_app_country] => US [patent_app_date] => 2003-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 8983 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/111/07111227.pdf [firstpage_image] =>[orig_patent_app_number] => 10728274 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 220523 [patent_doc_number] => 07613990 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-11-03 [patent_title] => 'Method and system for a multi-channel add-compare-select unit' [patent_app_type] => utility [patent_app_number] => 10/717042 [patent_app_country] => US [patent_app_date] => 2003-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7254 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/613/07613990.pdf [firstpage_image] =>[orig_patent_app_number] => 10717042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7477166 [patent_doc_number] => 20040098649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Test data generating system and method to test high-speed actual operation' [patent_app_type] => new [patent_app_number] => 10/704536 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9808 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20040098649.pdf [firstpage_image] =>[orig_patent_app_number] => 10704536 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 294195 [patent_doc_number] => 07546495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-09 [patent_title] => 'Method and device for managing defective storage units on a record carrier' [patent_app_type] => utility [patent_app_number] => 10/531019 [patent_app_country] => US [patent_app_date] => 2003-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1889 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/546/07546495.pdf [firstpage_image] =>[orig_patent_app_number] => 10531019 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 649126 [patent_doc_number] => 07120844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'System and method for performing scan test with single scan clock' [patent_app_type] => utility [patent_app_number] => 10/605031 [patent_app_country] => US [patent_app_date] => 2003-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2732 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/120/07120844.pdf [firstpage_image] =>[orig_patent_app_number] => 10605031 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 721886 [patent_doc_number] => 07055079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-30 [patent_title] => 'Liquid crystal display driving circuit, verifying apparatus and error tolerance method thereof' [patent_app_type] => utility [patent_app_number] => 10/605011 [patent_app_country] => US [patent_app_date] => 2003-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4014 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/055/07055079.pdf [firstpage_image] =>[orig_patent_app_number] => 10605011 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 799078 [patent_doc_number] => 07428672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-23 [patent_title] => 'Apparatus and methods for testing memory devices' [patent_app_type] => utility [patent_app_number] => 10/648311 [patent_app_country] => US [patent_app_date] => 2003-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6148 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/428/07428672.pdf [firstpage_image] =>[orig_patent_app_number] => 10648311 [rel_patent_id] =>[rel_patent_doc_number] =>)