Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7137356 [patent_doc_number] => 20040044491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Test circuit provided with built-in self test function' [patent_app_type] => new [patent_app_number] => 10/647378 [patent_app_country] => US [patent_app_date] => 2003-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5475 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20040044491.pdf [firstpage_image] =>[orig_patent_app_number] => 10647378 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/647378
Test circuit provided with built-in self test function Aug 25, 2003 Issued
Array ( [id] => 7418888 [patent_doc_number] => 20040177302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Apparatus for testing semiconductor integrated circuit' [patent_app_type] => new [patent_app_number] => 10/647267 [patent_app_country] => US [patent_app_date] => 2003-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 53 [patent_no_of_words] => 36609 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20040177302.pdf [firstpage_image] =>[orig_patent_app_number] => 10647267 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/647267
Apparatus for testing semiconductor integrated circuit Aug 25, 2003 Issued
Array ( [id] => 7084430 [patent_doc_number] => 20050049810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'METHOD AND SYSTEM FOR DETERMINING MINIMUM POST PRODUCTION TEST TIME REQUIRED ON AN INTEGRATED CIRCUIT DEVICE TO ACHIEVE OPTIMUM RELIABILITY' [patent_app_type] => utility [patent_app_number] => 10/604887 [patent_app_country] => US [patent_app_date] => 2003-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2652 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20050049810.pdf [firstpage_image] =>[orig_patent_app_number] => 10604887 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/604887
Method and system for determining minimum post production test time required on an integrated circuit device to achieve optimum reliability Aug 24, 2003 Issued
Array ( [id] => 340462 [patent_doc_number] => 07506227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-17 [patent_title] => 'Integrated circuit with embedded identification code' [patent_app_type] => utility [patent_app_number] => 10/525598 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2905 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/506/07506227.pdf [firstpage_image] =>[orig_patent_app_number] => 10525598 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/525598
Integrated circuit with embedded identification code Jul 30, 2003 Issued
Array ( [id] => 929654 [patent_doc_number] => 07315967 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-01 [patent_title] => 'Method and apparatus for automatic rate adaptation in a DOCSIS upstream' [patent_app_type] => utility [patent_app_number] => 10/632660 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9488 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/315/07315967.pdf [firstpage_image] =>[orig_patent_app_number] => 10632660 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/632660
Method and apparatus for automatic rate adaptation in a DOCSIS upstream Jul 30, 2003 Issued
Array ( [id] => 786141 [patent_doc_number] => 06993692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-31 [patent_title] => 'Method, system and apparatus for aggregating failures across multiple memories and applying a common defect repair solution to all of the multiple memories' [patent_app_type] => utility [patent_app_number] => 10/604195 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3226 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/993/06993692.pdf [firstpage_image] =>[orig_patent_app_number] => 10604195 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/604195
Method, system and apparatus for aggregating failures across multiple memories and applying a common defect repair solution to all of the multiple memories Jun 29, 2003 Issued
Array ( [id] => 7450006 [patent_doc_number] => 20040268195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'DIAGNOSABLE SCAN CHAIN' [patent_app_type] => new [patent_app_number] => 10/604194 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5372 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20040268195.pdf [firstpage_image] =>[orig_patent_app_number] => 10604194 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/604194
Diagnosable scan chain Jun 29, 2003 Issued
Array ( [id] => 626493 [patent_doc_number] => 07139949 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-21 [patent_title] => 'Test apparatus to facilitate building and testing complex computer products with contract manufacturers without proprietary information' [patent_app_type] => utility [patent_app_number] => 10/603900 [patent_app_country] => US [patent_app_date] => 2003-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 9951 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/139/07139949.pdf [firstpage_image] =>[orig_patent_app_number] => 10603900 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/603900
Test apparatus to facilitate building and testing complex computer products with contract manufacturers without proprietary information Jun 24, 2003 Issued
Array ( [id] => 731744 [patent_doc_number] => 07047476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Code error corrector' [patent_app_type] => utility [patent_app_number] => 10/464921 [patent_app_country] => US [patent_app_date] => 2003-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7457 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/047/07047476.pdf [firstpage_image] =>[orig_patent_app_number] => 10464921 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/464921
Code error corrector Jun 18, 2003 Issued
Array ( [id] => 508730 [patent_doc_number] => 07210081 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-04-24 [patent_title] => 'Apparatus and methods for assessing reliability of assemblies using programmable logic devices' [patent_app_type] => utility [patent_app_number] => 10/465139 [patent_app_country] => US [patent_app_date] => 2003-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6781 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/210/07210081.pdf [firstpage_image] =>[orig_patent_app_number] => 10465139 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/465139
Apparatus and methods for assessing reliability of assemblies using programmable logic devices Jun 18, 2003 Issued
Array ( [id] => 736371 [patent_doc_number] => 07043674 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-09 [patent_title] => 'Systems and methods for facilitating testing of pads of integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/464046 [patent_app_country] => US [patent_app_date] => 2003-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 7795 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/043/07043674.pdf [firstpage_image] =>[orig_patent_app_number] => 10464046 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/464046
Systems and methods for facilitating testing of pads of integrated circuits Jun 17, 2003 Issued
Array ( [id] => 7603541 [patent_doc_number] => 07117399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-03 [patent_title] => 'Method of and apparatus for controlling data storage system according to temperature, and medium' [patent_app_type] => utility [patent_app_number] => 10/463860 [patent_app_country] => US [patent_app_date] => 2003-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4700 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/117/07117399.pdf [firstpage_image] =>[orig_patent_app_number] => 10463860 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/463860
Method of and apparatus for controlling data storage system according to temperature, and medium Jun 17, 2003 Issued
Array ( [id] => 7402166 [patent_doc_number] => 20040039552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Signal sampling with sampling and reference paths' [patent_app_type] => new [patent_app_number] => 10/464185 [patent_app_country] => US [patent_app_date] => 2003-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3820 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20040039552.pdf [firstpage_image] =>[orig_patent_app_number] => 10464185 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/464185
Signal sampling with sampling and reference paths Jun 17, 2003 Issued
Array ( [id] => 466244 [patent_doc_number] => 07243296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-10 [patent_title] => 'Method of forward error correction' [patent_app_type] => utility [patent_app_number] => 10/518226 [patent_app_country] => US [patent_app_date] => 2003-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6663 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/243/07243296.pdf [firstpage_image] =>[orig_patent_app_number] => 10518226 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/518226
Method of forward error correction Jun 16, 2003 Issued
Array ( [id] => 4559751 [patent_doc_number] => 07877661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Method for encoding multiword information by wordwise interleaving and wordwise error protection with error locative clues derived from synchronizing channel bit groups and directed to target words, a method for decoding such information, a device for encoding and/or decoding such information, and a carrier provided with such information' [patent_app_type] => utility [patent_app_number] => 10/462197 [patent_app_country] => US [patent_app_date] => 2003-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/877/07877661.pdf [firstpage_image] =>[orig_patent_app_number] => 10462197 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/462197
Method for encoding multiword information by wordwise interleaving and wordwise error protection with error locative clues derived from synchronizing channel bit groups and directed to target words, a method for decoding such information, a device for encoding and/or decoding such information, and a carrier provided with such information Jun 15, 2003 Issued
Array ( [id] => 7333633 [patent_doc_number] => 20040255219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Time-aware best-effort hole-filling retry method and system for network communications' [patent_app_type] => new [patent_app_number] => 10/461797 [patent_app_country] => US [patent_app_date] => 2003-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7259 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20040255219.pdf [firstpage_image] =>[orig_patent_app_number] => 10461797 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/461797
Time-aware best-effort hole-filling retry method and system for network communications Jun 12, 2003 Issued
Array ( [id] => 7262513 [patent_doc_number] => 20040260991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Memory channel utilizing permuting status patterns' [patent_app_type] => new [patent_app_number] => 10/454400 [patent_app_country] => US [patent_app_date] => 2003-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12204 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20040260991.pdf [firstpage_image] =>[orig_patent_app_number] => 10454400 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/454400
Memory channel utilizing permuting status patterns Jun 2, 2003 Issued
Array ( [id] => 663171 [patent_doc_number] => 07107501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'Test device, test system and method for testing a memory circuit' [patent_app_type] => utility [patent_app_number] => 10/452485 [patent_app_country] => US [patent_app_date] => 2003-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5526 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/107/07107501.pdf [firstpage_image] =>[orig_patent_app_number] => 10452485 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/452485
Test device, test system and method for testing a memory circuit Jun 1, 2003 Issued
Array ( [id] => 7678184 [patent_doc_number] => 20030196152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-16 [patent_title] => 'Method of testing a circuit using an output vector' [patent_app_type] => new [patent_app_number] => 10/449452 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2372 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20030196152.pdf [firstpage_image] =>[orig_patent_app_number] => 10449452 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/449452
Method of testing a circuit using an output vector May 29, 2003 Issued
Array ( [id] => 7437409 [patent_doc_number] => 20040230880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Memory-Module Burn-In System With Removable Pattern-Generator Boards Separated from Heat Chamber by Backplane' [patent_app_type] => new [patent_app_number] => 10/249843 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3149 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20040230880.pdf [firstpage_image] =>[orig_patent_app_number] => 10249843 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/249843
Memory-module burn-in system with removable pattern-generator boards separated from heat chamber by backplane May 11, 2003 Issued
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