
Christine Trinh Le Tu
Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784 |
| Total Applications | 1748 |
| Issued Applications | 1571 |
| Pending Applications | 27 |
| Abandoned Applications | 152 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7321599
[patent_doc_number] => 20040225939
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-11
[patent_title] => 'BUILT-IN SELF TEST SYSTEM AND METHOD FOR TWO-DIMENSIONAL MEMORY REDUNDANCY ALLOCATION'
[patent_app_type] => new
[patent_app_number] => 10/249817
[patent_app_country] => US
[patent_app_date] => 2003-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 4460
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0225/20040225939.pdf
[firstpage_image] =>[orig_patent_app_number] => 10249817
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/249817 | Built-in self test system and method for two-dimensional memory redundancy allocation | May 8, 2003 | Issued |
Array
(
[id] => 7300594
[patent_doc_number] => 20040216011
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-28
[patent_title] => 'Extender Card with Intercepting EEPROM for Testing and Programming Un-Programmed Memory Modules on a PC Motherboard'
[patent_app_type] => new
[patent_app_number] => 10/249648
[patent_app_country] => US
[patent_app_date] => 2003-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5833
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0216/20040216011.pdf
[firstpage_image] =>[orig_patent_app_number] => 10249648
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/249648 | Extender card with intercepting EEPROM for testing and programming un-programmed memory modules on a PC motherboard | Apr 27, 2003 | Issued |
Array
(
[id] => 7608045
[patent_doc_number] => 07000155
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-14
[patent_title] => 'Redundancy register architecture for soft-error tolerance and methods of making the same'
[patent_app_type] => utility
[patent_app_number] => 10/249574
[patent_app_country] => US
[patent_app_date] => 2003-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3755
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/000/07000155.pdf
[firstpage_image] =>[orig_patent_app_number] => 10249574
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/249574 | Redundancy register architecture for soft-error tolerance and methods of making the same | Apr 20, 2003 | Issued |
Array
(
[id] => 953414
[patent_doc_number] => 06961886
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-11-01
[patent_title] => 'Diagnostic method for structural scan chain designs'
[patent_app_type] => utility
[patent_app_number] => 10/249513
[patent_app_country] => US
[patent_app_date] => 2003-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4530
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/961/06961886.pdf
[firstpage_image] =>[orig_patent_app_number] => 10249513
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/249513 | Diagnostic method for structural scan chain designs | Apr 15, 2003 | Issued |
Array
(
[id] => 582756
[patent_doc_number] => 07159159
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-02
[patent_title] => 'Circuit and method for adding parametric test capability to digital boundary scan'
[patent_app_type] => utility
[patent_app_number] => 10/414309
[patent_app_country] => US
[patent_app_date] => 2003-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 20
[patent_no_of_words] => 6870
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/159/07159159.pdf
[firstpage_image] =>[orig_patent_app_number] => 10414309
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/414309 | Circuit and method for adding parametric test capability to digital boundary scan | Apr 15, 2003 | Issued |
Array
(
[id] => 6615684
[patent_doc_number] => 20030210069
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-13
[patent_title] => 'Semiconductor device, and the method of testing or making of the semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/413135
[patent_app_country] => US
[patent_app_date] => 2003-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5555
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 36
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0210/20030210069.pdf
[firstpage_image] =>[orig_patent_app_number] => 10413135
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/413135 | Semiconductor device, and the method of testing or making of the semiconductor device | Apr 14, 2003 | Issued |
Array
(
[id] => 721884
[patent_doc_number] => 07055078
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-30
[patent_title] => 'Microprocessor with trace module'
[patent_app_type] => utility
[patent_app_number] => 10/412979
[patent_app_country] => US
[patent_app_date] => 2003-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2679
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/055/07055078.pdf
[firstpage_image] =>[orig_patent_app_number] => 10412979
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/412979 | Microprocessor with trace module | Apr 13, 2003 | Issued |
Array
(
[id] => 680288
[patent_doc_number] => 07089470
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-08-08
[patent_title] => 'Programmable test pattern and capture mechanism for boundary scan'
[patent_app_type] => utility
[patent_app_number] => 10/412192
[patent_app_country] => US
[patent_app_date] => 2003-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 5367
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/089/07089470.pdf
[firstpage_image] =>[orig_patent_app_number] => 10412192
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/412192 | Programmable test pattern and capture mechanism for boundary scan | Apr 10, 2003 | Issued |
Array
(
[id] => 7196876
[patent_doc_number] => 20040205431
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-14
[patent_title] => 'Method for testing jitter tolerance of high speed receivers'
[patent_app_type] => new
[patent_app_number] => 10/409949
[patent_app_country] => US
[patent_app_date] => 2003-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6873
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0205/20040205431.pdf
[firstpage_image] =>[orig_patent_app_number] => 10409949
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/409949 | Method for testing jitter tolerance of high speed receivers | Apr 8, 2003 | Issued |
Array
(
[id] => 7394611
[patent_doc_number] => 20040030973
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-02-12
[patent_title] => 'Method and apparatus for high update rate integrated circuit boundary scan'
[patent_app_type] => new
[patent_app_number] => 10/412718
[patent_app_country] => US
[patent_app_date] => 2003-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4217
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0030/20040030973.pdf
[firstpage_image] =>[orig_patent_app_number] => 10412718
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/412718 | Method and apparatus for high update rate integrated circuit boundary scan | Apr 8, 2003 | Issued |
Array
(
[id] => 7440999
[patent_doc_number] => 20040002832
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-01
[patent_title] => 'Method and apparatus for boundary scan of serial interfaces'
[patent_app_type] => new
[patent_app_number] => 10/412746
[patent_app_country] => US
[patent_app_date] => 2003-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4994
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0002/20040002832.pdf
[firstpage_image] =>[orig_patent_app_number] => 10412746
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/412746 | Method and apparatus for boundary scan of serial interfaces | Apr 8, 2003 | Abandoned |
Array
(
[id] => 7473017
[patent_doc_number] => 20040199844
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-07
[patent_title] => 'Test system including a test circuit board including resistive devices'
[patent_app_type] => new
[patent_app_number] => 10/408705
[patent_app_country] => US
[patent_app_date] => 2003-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3936
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0199/20040199844.pdf
[firstpage_image] =>[orig_patent_app_number] => 10408705
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/408705 | Test system including a test circuit board including resistive devices | Apr 6, 2003 | Issued |
Array
(
[id] => 6726403
[patent_doc_number] => 20030208715
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-06
[patent_title] => 'Apparatus and method for processing a corrupted frame'
[patent_app_type] => new
[patent_app_number] => 10/408497
[patent_app_country] => US
[patent_app_date] => 2003-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2542
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0208/20030208715.pdf
[firstpage_image] =>[orig_patent_app_number] => 10408497
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/408497 | Apparatus and method for processing a corrupted frame | Apr 6, 2003 | Issued |
Array
(
[id] => 1027746
[patent_doc_number] => 06886118
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-04-26
[patent_title] => 'Apparatus and method for filtering IP packets'
[patent_app_type] => utility
[patent_app_number] => 10/407006
[patent_app_country] => US
[patent_app_date] => 2003-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 4992
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/886/06886118.pdf
[firstpage_image] =>[orig_patent_app_number] => 10407006
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/407006 | Apparatus and method for filtering IP packets | Apr 3, 2003 | Issued |
Array
(
[id] => 7291197
[patent_doc_number] => 20040148553
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-29
[patent_title] => 'Scan controller and integrated circuit including such a controller'
[patent_app_type] => new
[patent_app_number] => 10/406872
[patent_app_country] => US
[patent_app_date] => 2003-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4526
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0148/20040148553.pdf
[firstpage_image] =>[orig_patent_app_number] => 10406872
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/406872 | Scan controller and integrated circuit including such a controller | Apr 3, 2003 | Issued |
Array
(
[id] => 599410
[patent_doc_number] => 07444567
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-10-28
[patent_title] => 'Method and apparatus for unifying self-test with scan-test during prototype debug and production test'
[patent_app_type] => utility
[patent_app_number] => 10/406592
[patent_app_country] => US
[patent_app_date] => 2003-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 12122
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/444/07444567.pdf
[firstpage_image] =>[orig_patent_app_number] => 10406592
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/406592 | Method and apparatus for unifying self-test with scan-test during prototype debug and production test | Apr 3, 2003 | Issued |
Array
(
[id] => 7393000
[patent_doc_number] => 20040017774
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-29
[patent_title] => 'Data transmission Method'
[patent_app_type] => new
[patent_app_number] => 10/407547
[patent_app_country] => US
[patent_app_date] => 2003-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2576
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0017/20040017774.pdf
[firstpage_image] =>[orig_patent_app_number] => 10407547
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/407547 | Data transmission method | Apr 3, 2003 | Issued |
Array
(
[id] => 7472817
[patent_doc_number] => 20040199809
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-07
[patent_title] => 'System and method for downloading files over a network with real time verification'
[patent_app_type] => new
[patent_app_number] => 10/406870
[patent_app_country] => US
[patent_app_date] => 2003-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4778
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0199/20040199809.pdf
[firstpage_image] =>[orig_patent_app_number] => 10406870
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/406870 | System and method for downloading files over a network with real time verification | Apr 3, 2003 | Issued |
Array
(
[id] => 537008
[patent_doc_number] => 07191370
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-13
[patent_title] => 'Data transmitter device, repeater device, data transmission/reception device, and data communication method'
[patent_app_type] => utility
[patent_app_number] => 10/501160
[patent_app_country] => US
[patent_app_date] => 2003-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 17
[patent_no_of_words] => 7206
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/191/07191370.pdf
[firstpage_image] =>[orig_patent_app_number] => 10501160
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/501160 | Data transmitter device, repeater device, data transmission/reception device, and data communication method | Mar 23, 2003 | Issued |
Array
(
[id] => 7175061
[patent_doc_number] => 20040078676
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-22
[patent_title] => 'AUTOMATIC COMPUTER-SYSTEM-LEVEL INTEGRATED CIRCUIT TESTING SYSTEM AND METHOD'
[patent_app_type] => new
[patent_app_number] => 10/249074
[patent_app_country] => US
[patent_app_date] => 2003-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4900
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0078/20040078676.pdf
[firstpage_image] =>[orig_patent_app_number] => 10249074
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/249074 | AUTOMATIC COMPUTER-SYSTEM-LEVEL INTEGRATED CIRCUIT TESTING SYSTEM AND METHOD | Mar 13, 2003 | Abandoned |