Search

Christine Trinh Le Tu

Examiner (ID: 6386, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2133, 2117, 2111, 2313, 2784, 2785, 2138, 2413
Total Applications
1773
Issued Applications
1557
Pending Applications
64
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4382156 [patent_doc_number] => 06261971 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method of manufacturing a semiconductor device by thermal oxidation of amorphous semiconductor film' [patent_app_type] => 1 [patent_app_number] => 9/313081 [patent_app_country] => US [patent_app_date] => 1999-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 29 [patent_no_of_words] => 7212 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261971.pdf [firstpage_image] =>[orig_patent_app_number] => 313081 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/313081
Method of manufacturing a semiconductor device by thermal oxidation of amorphous semiconductor film May 16, 1999 Issued
Array ( [id] => 4290037 [patent_doc_number] => 06235614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Methods of crystallizing amorphous silicon layer and fabricating thin film transistor using the same' [patent_app_type] => 1 [patent_app_number] => 9/311711 [patent_app_country] => US [patent_app_date] => 1999-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2899 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235614.pdf [firstpage_image] =>[orig_patent_app_number] => 311711 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/311711
Methods of crystallizing amorphous silicon layer and fabricating thin film transistor using the same May 12, 1999 Issued
Array ( [id] => 1536198 [patent_doc_number] => 06337280 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Polishing cloth and method of manufacturing semiconductor device using the same' [patent_app_type] => B1 [patent_app_number] => 09/306758 [patent_app_country] => US [patent_app_date] => 1999-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 6433 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/337/06337280.pdf [firstpage_image] =>[orig_patent_app_number] => 09306758 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/306758
Polishing cloth and method of manufacturing semiconductor device using the same May 6, 1999 Issued
Array ( [id] => 4302871 [patent_doc_number] => 06187657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Dual material gate MOSFET technique' [patent_app_type] => 1 [patent_app_number] => 9/275486 [patent_app_country] => US [patent_app_date] => 1999-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4275 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/187/06187657.pdf [firstpage_image] =>[orig_patent_app_number] => 275486 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/275486
Dual material gate MOSFET technique Mar 23, 1999 Issued
Array ( [id] => 4318406 [patent_doc_number] => 06248614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Flip-chip package with optimized encapsulant adhesion and method' [patent_app_type] => 1 [patent_app_number] => 9/272518 [patent_app_country] => US [patent_app_date] => 1999-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3498 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/248/06248614.pdf [firstpage_image] =>[orig_patent_app_number] => 272518 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/272518
Flip-chip package with optimized encapsulant adhesion and method Mar 18, 1999 Issued
Array ( [id] => 4408136 [patent_doc_number] => 06300183 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method therefor' [patent_app_type] => 1 [patent_app_number] => 9/272675 [patent_app_country] => US [patent_app_date] => 1999-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3933 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300183.pdf [firstpage_image] =>[orig_patent_app_number] => 272675 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/272675
Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method therefor Mar 18, 1999 Issued
Array ( [id] => 4267029 [patent_doc_number] => 06306728 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Stable high voltage semiconductor device structure' [patent_app_type] => 1 [patent_app_number] => 9/268858 [patent_app_country] => US [patent_app_date] => 1999-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 5239 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306728.pdf [firstpage_image] =>[orig_patent_app_number] => 268858 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/268858
Stable high voltage semiconductor device structure Mar 14, 1999 Issued
Array ( [id] => 4354107 [patent_doc_number] => 06218270 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method of manufacturing semiconductor device having shallow junction' [patent_app_type] => 1 [patent_app_number] => 9/261223 [patent_app_country] => US [patent_app_date] => 1999-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 4512 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218270.pdf [firstpage_image] =>[orig_patent_app_number] => 261223 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/261223
Method of manufacturing semiconductor device having shallow junction Mar 2, 1999 Issued
Array ( [id] => 4367111 [patent_doc_number] => 06274511 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of refractory metal layer' [patent_app_type] => 1 [patent_app_number] => 9/256781 [patent_app_country] => US [patent_app_date] => 1999-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3702 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274511.pdf [firstpage_image] =>[orig_patent_app_number] => 256781 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/256781
Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of refractory metal layer Feb 23, 1999 Issued
Array ( [id] => 4270190 [patent_doc_number] => 06245649 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Method for forming a retrograde impurity profile' [patent_app_type] => 1 [patent_app_number] => 9/251923 [patent_app_country] => US [patent_app_date] => 1999-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2691 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/245/06245649.pdf [firstpage_image] =>[orig_patent_app_number] => 251923 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/251923
Method for forming a retrograde impurity profile Feb 16, 1999 Issued
Array ( [id] => 4347824 [patent_doc_number] => 06214675 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Method for fabricating a merged integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 9/246402 [patent_app_country] => US [patent_app_date] => 1999-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4127 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214675.pdf [firstpage_image] =>[orig_patent_app_number] => 246402 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/246402
Method for fabricating a merged integrated circuit device Feb 7, 1999 Issued
Array ( [id] => 4286394 [patent_doc_number] => 06268233 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Photovoltaic device' [patent_app_type] => 1 [patent_app_number] => 9/232702 [patent_app_country] => US [patent_app_date] => 1999-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 10192 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268233.pdf [firstpage_image] =>[orig_patent_app_number] => 232702 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/232702
Photovoltaic device Jan 18, 1999 Issued
Array ( [id] => 4358734 [patent_doc_number] => 06255203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Technique for low-temperature formation of excellent silicided .alpha.-Si gate structures' [patent_app_type] => 1 [patent_app_number] => 9/216672 [patent_app_country] => US [patent_app_date] => 1998-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2018 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255203.pdf [firstpage_image] =>[orig_patent_app_number] => 216672 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/216672
Technique for low-temperature formation of excellent silicided .alpha.-Si gate structures Dec 15, 1998 Issued
Array ( [id] => 4292389 [patent_doc_number] => 06180488 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Method of forming separating region of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/196766 [patent_app_country] => US [patent_app_date] => 1998-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 2832 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/180/06180488.pdf [firstpage_image] =>[orig_patent_app_number] => 196766 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/196766
Method of forming separating region of semiconductor device Nov 19, 1998 Issued
Array ( [id] => 4286855 [patent_doc_number] => 06268263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Method of forming a trench type element isolation in semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 9/196134 [patent_app_country] => US [patent_app_date] => 1998-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 35 [patent_no_of_words] => 10265 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268263.pdf [firstpage_image] =>[orig_patent_app_number] => 196134 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/196134
Method of forming a trench type element isolation in semiconductor substrate Nov 19, 1998 Issued
Array ( [id] => 4357546 [patent_doc_number] => 06190998 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Method for achieving a thin film of solid material and applications of this method' [patent_app_type] => 1 [patent_app_number] => 9/147266 [patent_app_country] => US [patent_app_date] => 1998-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3143 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/190/06190998.pdf [firstpage_image] =>[orig_patent_app_number] => 147266 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/147266
Method for achieving a thin film of solid material and applications of this method Nov 15, 1998 Issued
Array ( [id] => 4350754 [patent_doc_number] => 06291327 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Optimization of S/D annealing to minimize S/D shorts in memory array' [patent_app_type] => 1 [patent_app_number] => 9/192094 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3107 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291327.pdf [firstpage_image] =>[orig_patent_app_number] => 192094 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/192094
Optimization of S/D annealing to minimize S/D shorts in memory array Nov 12, 1998 Issued
Array ( [id] => 4353832 [patent_doc_number] => 06218251 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Asymmetrical IGFET devices with spacers formed by HDP techniques' [patent_app_type] => 1 [patent_app_number] => 9/187894 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2930 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218251.pdf [firstpage_image] =>[orig_patent_app_number] => 187894 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187894
Asymmetrical IGFET devices with spacers formed by HDP techniques Nov 5, 1998 Issued
Array ( [id] => 4286157 [patent_doc_number] => 06211032 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Method for forming silicon carbide chrome thin-film resistor' [patent_app_type] => 1 [patent_app_number] => 9/187244 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 21 [patent_no_of_words] => 5160 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211032.pdf [firstpage_image] =>[orig_patent_app_number] => 187244 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187244
Method for forming silicon carbide chrome thin-film resistor Nov 5, 1998 Issued
Array ( [id] => 4286827 [patent_doc_number] => 06268261 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Microprocessor having air as a dielectric and encapsulated lines and process for manufacture' [patent_app_type] => 1 [patent_app_number] => 9/185185 [patent_app_country] => US [patent_app_date] => 1998-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 21 [patent_no_of_words] => 3847 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268261.pdf [firstpage_image] =>[orig_patent_app_number] => 185185 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/185185
Microprocessor having air as a dielectric and encapsulated lines and process for manufacture Nov 2, 1998 Issued
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