Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7042626 [patent_doc_number] => 20050160338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Integrated circuit with test circuit' [patent_app_type] => utility [patent_app_number] => 10/506234 [patent_app_country] => US [patent_app_date] => 2003-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2394 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20050160338.pdf [firstpage_image] =>[orig_patent_app_number] => 10506234 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/506234
Integrated circuit with test circuit Feb 25, 2003 Issued
Array ( [id] => 757979 [patent_doc_number] => 07024608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Transmitting method and transmitting apparatus' [patent_app_type] => utility [patent_app_number] => 10/508677 [patent_app_country] => US [patent_app_date] => 2003-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 6567 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/024/07024608.pdf [firstpage_image] =>[orig_patent_app_number] => 10508677 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/508677
Transmitting method and transmitting apparatus Feb 18, 2003 Issued
Array ( [id] => 778005 [patent_doc_number] => 07003708 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-21 [patent_title] => 'Method and apparatus for generating bit errors with a poisson error distribution' [patent_app_type] => utility [patent_app_number] => 10/365877 [patent_app_country] => US [patent_app_date] => 2003-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3100 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/003/07003708.pdf [firstpage_image] =>[orig_patent_app_number] => 10365877 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/365877
Method and apparatus for generating bit errors with a poisson error distribution Feb 12, 2003 Issued
Array ( [id] => 6679694 [patent_doc_number] => 20030229835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-11 [patent_title] => 'High speed interconnect circuit test method and apparatus' [patent_app_type] => new [patent_app_number] => 10/364100 [patent_app_country] => US [patent_app_date] => 2003-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13645 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20030229835.pdf [firstpage_image] =>[orig_patent_app_number] => 10364100 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/364100
High speed interconnect circuit test method and apparatus Feb 10, 2003 Issued
Array ( [id] => 937675 [patent_doc_number] => 06976196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-13 [patent_title] => 'Error detecting method and device, information storing and reproducing device and magnetic disk drive' [patent_app_type] => utility [patent_app_number] => 10/364746 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 10591 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/976/06976196.pdf [firstpage_image] =>[orig_patent_app_number] => 10364746 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/364746
Error detecting method and device, information storing and reproducing device and magnetic disk drive Feb 9, 2003 Issued
Array ( [id] => 705376 [patent_doc_number] => 07069487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'Pattern matching to validate and classify computer variables to one or more name ranges' [patent_app_type] => utility [patent_app_number] => 10/361247 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2934 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/069/07069487.pdf [firstpage_image] =>[orig_patent_app_number] => 10361247 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/361247
Pattern matching to validate and classify computer variables to one or more name ranges Feb 9, 2003 Issued
Array ( [id] => 7226602 [patent_doc_number] => 20040156396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Data transmission update technique in low power modes' [patent_app_type] => new [patent_app_number] => 10/360312 [patent_app_country] => US [patent_app_date] => 2003-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2799 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20040156396.pdf [firstpage_image] =>[orig_patent_app_number] => 10360312 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/360312
Data transmission update technique in low power modes Feb 6, 2003 Issued
Array ( [id] => 7247290 [patent_doc_number] => 20040158786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Concurrently programmable dynamic memory built-in self-test (BIST)' [patent_app_type] => new [patent_app_number] => 10/360959 [patent_app_country] => US [patent_app_date] => 2003-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3170 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20040158786.pdf [firstpage_image] =>[orig_patent_app_number] => 10360959 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/360959
Concurrently programmable dynamic memory built-in self-test (BIST) Feb 6, 2003 Issued
Array ( [id] => 7679223 [patent_doc_number] => 20030167429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-04 [patent_title] => 'Boundary scan with mode control cells' [patent_app_type] => new [patent_app_number] => 10/359301 [patent_app_country] => US [patent_app_date] => 2003-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5907 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20030167429.pdf [firstpage_image] =>[orig_patent_app_number] => 10359301 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/359301
Boundary scan with mode control cells Feb 5, 2003 Abandoned
Array ( [id] => 757995 [patent_doc_number] => 07024613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Method and apparatus for implementing infiniband transmit queue' [patent_app_type] => utility [patent_app_number] => 10/359777 [patent_app_country] => US [patent_app_date] => 2003-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4402 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/024/07024613.pdf [firstpage_image] =>[orig_patent_app_number] => 10359777 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/359777
Method and apparatus for implementing infiniband transmit queue Feb 5, 2003 Issued
Array ( [id] => 7679219 [patent_doc_number] => 20030167433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-04 [patent_title] => 'Hybrid ARQ retransmission method with reduced buffer size requirement and receiver therefor' [patent_app_type] => new [patent_app_number] => 10/358386 [patent_app_country] => US [patent_app_date] => 2003-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4320 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20030167433.pdf [firstpage_image] =>[orig_patent_app_number] => 10358386 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/358386
Hybrid ARQ retransmission method with reduced buffer size requirement and receiver therefor Feb 4, 2003 Issued
Array ( [id] => 7675911 [patent_doc_number] => 20040153916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Apparatus and method for testing integrated circuits using weighted pseudo-random test patterns' [patent_app_type] => new [patent_app_number] => 10/358461 [patent_app_country] => US [patent_app_date] => 2003-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5193 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20040153916.pdf [firstpage_image] =>[orig_patent_app_number] => 10358461 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/358461
Circuit apparatus and method for testing integrated circuits using weighted pseudo-random test patterns Feb 3, 2003 Issued
Array ( [id] => 6857797 [patent_doc_number] => 20030131298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'Test pattern compression for an integrated circuit test environment' [patent_app_type] => new [patent_app_number] => 10/355941 [patent_app_country] => US [patent_app_date] => 2003-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8105 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20030131298.pdf [firstpage_image] =>[orig_patent_app_number] => 10355941 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/355941
Test pattern compression for an integrated circuit test environment Jan 30, 2003 Issued
Array ( [id] => 6670536 [patent_doc_number] => 20030115521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Method and apparatus for selectively compacting test responses' [patent_app_type] => new [patent_app_number] => 10/354576 [patent_app_country] => US [patent_app_date] => 2003-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5158 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20030115521.pdf [firstpage_image] =>[orig_patent_app_number] => 10354576 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/354576
Method and apparatus for selectively compacting test responses Jan 28, 2003 Issued
Array ( [id] => 962294 [patent_doc_number] => 06952796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-04 [patent_title] => 'Test data generating system and method to test high-speed actual operation' [patent_app_type] => utility [patent_app_number] => 10/352986 [patent_app_country] => US [patent_app_date] => 2003-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 9653 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/952/06952796.pdf [firstpage_image] =>[orig_patent_app_number] => 10352986 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/352986
Test data generating system and method to test high-speed actual operation Jan 28, 2003 Issued
Array ( [id] => 736415 [patent_doc_number] => 07043684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-09 [patent_title] => 'Method for the synchronization of two digital data flows with identical content' [patent_app_type] => utility [patent_app_number] => 10/502379 [patent_app_country] => US [patent_app_date] => 2003-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7894 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/043/07043684.pdf [firstpage_image] =>[orig_patent_app_number] => 10502379 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/502379
Method for the synchronization of two digital data flows with identical content Jan 22, 2003 Issued
Array ( [id] => 739883 [patent_doc_number] => 07039844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-02 [patent_title] => 'Integrated circuit with self-testing circuit' [patent_app_type] => utility [patent_app_number] => 10/501796 [patent_app_country] => US [patent_app_date] => 2003-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2245 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/039/07039844.pdf [firstpage_image] =>[orig_patent_app_number] => 10501796 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/501796
Integrated circuit with self-testing circuit Jan 13, 2003 Issued
Array ( [id] => 7260502 [patent_doc_number] => 20050076278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => 'Testing of circuit with plural clock domains' [patent_app_type] => utility [patent_app_number] => 10/502825 [patent_app_country] => US [patent_app_date] => 2003-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3415 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20050076278.pdf [firstpage_image] =>[orig_patent_app_number] => 10502825 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/502825
Testing of circuit with plural clock domains Dec 22, 2002 Issued
Array ( [id] => 987818 [patent_doc_number] => 06925588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-02 [patent_title] => 'Methods and apparatus for testing data lines' [patent_app_type] => utility [patent_app_number] => 10/328699 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4490 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/925/06925588.pdf [firstpage_image] =>[orig_patent_app_number] => 10328699 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/328699
Methods and apparatus for testing data lines Dec 22, 2002 Issued
Array ( [id] => 7477144 [patent_doc_number] => 20040123193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Method and apparatus for enhanced parallel port JTAG interface' [patent_app_type] => new [patent_app_number] => 10/325734 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2597 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20040123193.pdf [firstpage_image] =>[orig_patent_app_number] => 10325734 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/325734
Method and apparatus for enhanced parallel port JTAG interface Dec 22, 2002 Issued
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