Christine Trinh Le Tu

Array ( [id] => 667088 [patent_doc_number] => 07103811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Mechanisms for detecting silent errors in streaming media devices' [patent_app_type] => utility [patent_app_number] => 10/328792 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3030 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/103/07103811.pdf [firstpage_image] =>[orig_patent_app_number] => 10328792 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 645681 [patent_doc_number] => 07124337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Data storage apparatus and method for handling data on a data storage apparatus' [patent_app_type] => utility [patent_app_number] => 10/502526 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6380 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/124/07124337.pdf [firstpage_image] =>[orig_patent_app_number] => 10502526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7673525 [patent_doc_number] => 20040128593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Fault repair controller for redundant memory integrated circuits' [patent_app_type] => new [patent_app_number] => 10/328700 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10138 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20040128593.pdf [firstpage_image] =>[orig_patent_app_number] => 10328700 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 726400 [patent_doc_number] => 07051255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-23 [patent_title] => 'Method and apparatus for reducing power dissipation in latches during scan operation' [patent_app_type] => utility [patent_app_number] => 10/326784 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4006 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/051/07051255.pdf [firstpage_image] =>[orig_patent_app_number] => 10326784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 762110 [patent_doc_number] => 07020820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-28 [patent_title] => 'Instruction-based built-in self-test (BIST) of external memory' [patent_app_type] => utility [patent_app_number] => 10/326630 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5585 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/020/07020820.pdf [firstpage_image] =>[orig_patent_app_number] => 10326630 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7477131 [patent_doc_number] => 20040123181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Self-repair of memory arrays using preallocated redundancy (PAR) architecture' [patent_app_type] => new [patent_app_number] => 10/327641 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4128 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20040123181.pdf [firstpage_image] =>[orig_patent_app_number] => 10327641 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 984789 [patent_doc_number] => 06928606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'Fault tolerant scan chain for a parallel processing system' [patent_app_type] => utility [patent_app_number] => 10/323896 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5909 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/928/06928606.pdf [firstpage_image] =>[orig_patent_app_number] => 10323896 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 721847 [patent_doc_number] => 07055060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-30 [patent_title] => 'On-die mechanism for high-reliability processor' [patent_app_type] => utility [patent_app_number] => 10/324957 [patent_app_country] => US [patent_app_date] => 2002-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5421 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/055/07055060.pdf [firstpage_image] =>[orig_patent_app_number] => 10324957 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 626503 [patent_doc_number] => 07139955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-21 [patent_title] => 'Hierarchically-controlled automatic test pattern generation' [patent_app_type] => utility [patent_app_number] => 10/321758 [patent_app_country] => US [patent_app_date] => 2002-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8077 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/139/07139955.pdf [firstpage_image] =>[orig_patent_app_number] => 10321758 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 590814 [patent_doc_number] => 07464324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Method and apparatus for forward error correction coding for an AM in-band on-channel digital audio broadcasting system' [patent_app_type] => utility [patent_app_number] => 10/310105 [patent_app_country] => US [patent_app_date] => 2002-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 9806 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/464/07464324.pdf [firstpage_image] =>[orig_patent_app_number] => 10310105 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7271470 [patent_doc_number] => 20040059988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Transmission apparatus, reception apparatus, transmission method, and reception method' [patent_app_type] => new [patent_app_number] => 10/466103 [patent_app_country] => US [patent_app_date] => 2003-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7530 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20040059988.pdf [firstpage_image] =>[orig_patent_app_number] => 10466103 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1004793 [patent_doc_number] => 06910166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-21 [patent_title] => 'Method of and apparatus for timing verification of LSI test data and computer product' [patent_app_type] => utility [patent_app_number] => 10/253713 [patent_app_country] => US [patent_app_date] => 2002-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4235 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/910/06910166.pdf [firstpage_image] =>[orig_patent_app_number] => 10253713 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6675952 [patent_doc_number] => 20030061555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => new [patent_app_number] => 10/252719 [patent_app_country] => US [patent_app_date] => 2002-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3313 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20030061555.pdf [firstpage_image] =>[orig_patent_app_number] => 10252719 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 706942 [patent_doc_number] => 07065687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Method for replacing defective memory cells in data processing apparatus' [patent_app_type] => utility [patent_app_number] => 10/253465 [patent_app_country] => US [patent_app_date] => 2002-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2202 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/065/07065687.pdf [firstpage_image] =>[orig_patent_app_number] => 10253465 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7175247 [patent_doc_number] => 20040078713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Interface circuit' [patent_app_type] => new [patent_app_number] => 10/252687 [patent_app_country] => US [patent_app_date] => 2002-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7890 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20040078713.pdf [firstpage_image] =>[orig_patent_app_number] => 10252687 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1017336 [patent_doc_number] => 06895536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-17 [patent_title] => 'Testable up down counter for use in a logic analyzer' [patent_app_type] => utility [patent_app_number] => 10/253620 [patent_app_country] => US [patent_app_date] => 2002-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1622 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/895/06895536.pdf [firstpage_image] =>[orig_patent_app_number] => 10253620 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 943683 [patent_doc_number] => 06971055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-29 [patent_title] => 'Method for verifying the accuracy of bit-map memory test programs' [patent_app_type] => utility [patent_app_number] => 10/251963 [patent_app_country] => US [patent_app_date] => 2002-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1620 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/971/06971055.pdf [firstpage_image] =>[orig_patent_app_number] => 10251963 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6871706 [patent_doc_number] => 20030084396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'D/A conversion apparatus, decoder, and tape drive' [patent_app_type] => new [patent_app_number] => 10/251105 [patent_app_country] => US [patent_app_date] => 2002-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11035 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20030084396.pdf [firstpage_image] =>[orig_patent_app_number] => 10251105 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1004798 [patent_doc_number] => 06910169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-21 [patent_title] => 'ECC code mechanism to detect wire stuck-at faults' [patent_app_type] => utility [patent_app_number] => 10/245260 [patent_app_country] => US [patent_app_date] => 2002-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 4884 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/910/06910169.pdf [firstpage_image] =>[orig_patent_app_number] => 10245260 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1052662 [patent_doc_number] => 06862704 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-01 [patent_title] => 'Apparatus and method for testing memory in a microprocessor' [patent_app_type] => utility [patent_app_number] => 10/236789 [patent_app_country] => US [patent_app_date] => 2002-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8836 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/862/06862704.pdf [firstpage_image] =>[orig_patent_app_number] => 10236789 [rel_patent_id] =>[rel_patent_doc_number] =>)