Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6419782 [patent_doc_number] => 20020183981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Turbo decoding apparatus and decoding iteration count controlling method in turbo decoding' [patent_app_type] => new [patent_app_number] => 10/142776 [patent_app_country] => US [patent_app_date] => 2002-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4559 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20020183981.pdf [firstpage_image] =>[orig_patent_app_number] => 10142776 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/142776
Turbo decoding apparatus and decoding iteration count controlling method in turbo decoding May 12, 2002 Issued
Array ( [id] => 762167 [patent_doc_number] => 07020835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-28 [patent_title] => 'Enhancements to data integrity verification mechanism' [patent_app_type] => utility [patent_app_number] => 10/133002 [patent_app_country] => US [patent_app_date] => 2002-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8532 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/020/07020835.pdf [firstpage_image] =>[orig_patent_app_number] => 10133002 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/133002
Enhancements to data integrity verification mechanism Apr 24, 2002 Issued
Array ( [id] => 6161643 [patent_doc_number] => 20020147950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'Method and apparatus for test connectivity, communication, and control' [patent_app_type] => new [patent_app_number] => 10/114193 [patent_app_country] => US [patent_app_date] => 2002-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 22361 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20020147950.pdf [firstpage_image] =>[orig_patent_app_number] => 10114193 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/114193
Tap and test controller with separate enable inputs Apr 1, 2002 Issued
Array ( [id] => 6562580 [patent_doc_number] => 20020138798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Configuration for testing an integrated semiconductor memory and method for testing the memory' [patent_app_type] => new [patent_app_number] => 10/106591 [patent_app_country] => US [patent_app_date] => 2002-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2876 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20020138798.pdf [firstpage_image] =>[orig_patent_app_number] => 10106591 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/106591
Configuration for testing an integrated semiconductor memory and method for testing the memory Mar 25, 2002 Issued
Array ( [id] => 6717487 [patent_doc_number] => 20030028835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => new [patent_app_number] => 10/102709 [patent_app_country] => US [patent_app_date] => 2002-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11597 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20030028835.pdf [firstpage_image] =>[orig_patent_app_number] => 10102709 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/102709
Semiconductor integrated circuit Mar 21, 2002 Abandoned
Array ( [id] => 1037218 [patent_doc_number] => 06877120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-05 [patent_title] => 'Method of acquiring scan chain reorder information, and computer product' [patent_app_type] => utility [patent_app_number] => 10/101271 [patent_app_country] => US [patent_app_date] => 2002-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2955 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/877/06877120.pdf [firstpage_image] =>[orig_patent_app_number] => 10101271 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/101271
Method of acquiring scan chain reorder information, and computer product Mar 19, 2002 Issued
Array ( [id] => 5785116 [patent_doc_number] => 20020159454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'Method of protecting data packets against errors' [patent_app_type] => new [patent_app_number] => 10/095550 [patent_app_country] => US [patent_app_date] => 2002-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2841 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20020159454.pdf [firstpage_image] =>[orig_patent_app_number] => 10095550 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/095550
Method of protecting data packets against errors Mar 11, 2002 Abandoned
Array ( [id] => 6775600 [patent_doc_number] => 20030018938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Test pattern generation circuit and method for use with self-diagnostic circuit' [patent_app_type] => new [patent_app_number] => 10/059118 [patent_app_country] => US [patent_app_date] => 2002-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2283 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20030018938.pdf [firstpage_image] =>[orig_patent_app_number] => 10059118 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/059118
Test pattern generation circuit and method for use with self-diagnostic circuit Jan 30, 2002 Issued
Array ( [id] => 7608036 [patent_doc_number] => 07000164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-14 [patent_title] => 'Method for scan testing and clocking dynamic domino circuits in VLSI systems using level sensitive latches and edge triggered flip flops' [patent_app_type] => utility [patent_app_number] => 10/060179 [patent_app_country] => US [patent_app_date] => 2002-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15524 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/000/07000164.pdf [firstpage_image] =>[orig_patent_app_number] => 10060179 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/060179
Method for scan testing and clocking dynamic domino circuits in VLSI systems using level sensitive latches and edge triggered flip flops Jan 29, 2002 Issued
Array ( [id] => 1007745 [patent_doc_number] => 06907556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-14 [patent_title] => 'Scanable R-S glitch latch for dynamic circuits' [patent_app_type] => utility [patent_app_number] => 10/060716 [patent_app_country] => US [patent_app_date] => 2002-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7512 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/907/06907556.pdf [firstpage_image] =>[orig_patent_app_number] => 10060716 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/060716
Scanable R-S glitch latch for dynamic circuits Jan 29, 2002 Issued
Array ( [id] => 978882 [patent_doc_number] => 06934899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-23 [patent_title] => 'Variable self-time scheme for write recovery by low speed tester' [patent_app_type] => utility [patent_app_number] => 10/060481 [patent_app_country] => US [patent_app_date] => 2002-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3677 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/934/06934899.pdf [firstpage_image] =>[orig_patent_app_number] => 10060481 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/060481
Variable self-time scheme for write recovery by low speed tester Jan 29, 2002 Issued
Array ( [id] => 6675950 [patent_doc_number] => 20030061553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Control apparatus for controlling recovery of terminal-station apparatus from abnormality' [patent_app_type] => new [patent_app_number] => 10/060594 [patent_app_country] => US [patent_app_date] => 2002-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10713 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20030061553.pdf [firstpage_image] =>[orig_patent_app_number] => 10060594 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/060594
Control apparatus for controlling recovery of terminal-station apparatus from abnormality Jan 29, 2002 Issued
Array ( [id] => 1040090 [patent_doc_number] => 06874112 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-29 [patent_title] => 'Fault coverage and simplified test pattern generation for integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/059831 [patent_app_country] => US [patent_app_date] => 2002-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 6 [patent_no_of_words] => 6458 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/874/06874112.pdf [firstpage_image] =>[orig_patent_app_number] => 10059831 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/059831
Fault coverage and simplified test pattern generation for integrated circuits Jan 27, 2002 Issued
Array ( [id] => 1071043 [patent_doc_number] => 06845480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-18 [patent_title] => 'Test pattern generator and test pattern generation' [patent_app_type] => utility [patent_app_number] => 10/058683 [patent_app_country] => US [patent_app_date] => 2002-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3511 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/845/06845480.pdf [firstpage_image] =>[orig_patent_app_number] => 10058683 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/058683
Test pattern generator and test pattern generation Jan 27, 2002 Issued
Array ( [id] => 1106355 [patent_doc_number] => 06816990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'VLSI chip test power reduction' [patent_app_type] => B2 [patent_app_number] => 10/058485 [patent_app_country] => US [patent_app_date] => 2002-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2960 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/816/06816990.pdf [firstpage_image] =>[orig_patent_app_number] => 10058485 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/058485
VLSI chip test power reduction Jan 27, 2002 Issued
Array ( [id] => 1116712 [patent_doc_number] => 06800817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-05 [patent_title] => 'Semiconductor component for connection to a test system' [patent_app_type] => B2 [patent_app_number] => 10/055522 [patent_app_country] => US [patent_app_date] => 2002-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2451 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/800/06800817.pdf [firstpage_image] =>[orig_patent_app_number] => 10055522 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/055522
Semiconductor component for connection to a test system Jan 22, 2002 Issued
Array ( [id] => 7609986 [patent_doc_number] => 06842873 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-11 [patent_title] => 'Advanced forward error correction' [patent_app_type] => utility [patent_app_number] => 10/057774 [patent_app_country] => US [patent_app_date] => 2002-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5351 [patent_no_of_claims] => 80 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/842/06842873.pdf [firstpage_image] =>[orig_patent_app_number] => 10057774 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/057774
Advanced forward error correction Jan 21, 2002 Issued
Array ( [id] => 1166951 [patent_doc_number] => 06772381 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-03 [patent_title] => 'Programmable logic device verification system and method' [patent_app_type] => B1 [patent_app_number] => 10/051791 [patent_app_country] => US [patent_app_date] => 2002-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2668 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/772/06772381.pdf [firstpage_image] =>[orig_patent_app_number] => 10051791 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/051791
Programmable logic device verification system and method Jan 16, 2002 Issued
Array ( [id] => 7613781 [patent_doc_number] => 06898750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'In-chip monitoring system to monitor input/output of functional blocks' [patent_app_type] => utility [patent_app_number] => 10/052063 [patent_app_country] => US [patent_app_date] => 2002-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3055 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/898/06898750.pdf [firstpage_image] =>[orig_patent_app_number] => 10052063 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/052063
In-chip monitoring system to monitor input/output of functional blocks Jan 15, 2002 Issued
Array ( [id] => 7618381 [patent_doc_number] => 06944812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Mode entry circuit and method' [patent_app_type] => utility [patent_app_number] => 10/050404 [patent_app_country] => US [patent_app_date] => 2002-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3634 [patent_no_of_claims] => 71 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/944/06944812.pdf [firstpage_image] =>[orig_patent_app_number] => 10050404 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/050404
Mode entry circuit and method Jan 14, 2002 Issued
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