Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6369733 [patent_doc_number] => 20020059549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Digital data recording channel' [patent_app_type] => new [patent_app_number] => 10/041537 [patent_app_country] => US [patent_app_date] => 2002-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11658 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20020059549.pdf [firstpage_image] =>[orig_patent_app_number] => 10041537 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/041537
Digital data recording channel Jan 6, 2002 Issued
Array ( [id] => 5848555 [patent_doc_number] => 20020133769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'Circuit and method for test and repair' [patent_app_type] => new [patent_app_number] => 10/022436 [patent_app_country] => US [patent_app_date] => 2001-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11988 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20020133769.pdf [firstpage_image] =>[orig_patent_app_number] => 10022436 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/022436
Circuit and method for test and repair Dec 11, 2001 Abandoned
Array ( [id] => 6670541 [patent_doc_number] => 20030115526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Method of optimizing test development for digital circuits' [patent_app_type] => new [patent_app_number] => 10/017649 [patent_app_country] => US [patent_app_date] => 2001-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 18296 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20030115526.pdf [firstpage_image] =>[orig_patent_app_number] => 10017649 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/017649
Method for optimizing test development for digital circuits Dec 11, 2001 Issued
Array ( [id] => 778014 [patent_doc_number] => 07003712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Apparatus and method for adaptive, multimode decoding' [patent_app_type] => utility [patent_app_number] => 09/996661 [patent_app_country] => US [patent_app_date] => 2001-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 10282 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/003/07003712.pdf [firstpage_image] =>[orig_patent_app_number] => 09996661 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/996661
Apparatus and method for adaptive, multimode decoding Nov 28, 2001 Issued
Array ( [id] => 1100502 [patent_doc_number] => 06823487 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-23 [patent_title] => 'Method and apparatus for enhancing correction power of reverse order error correction codes' [patent_app_type] => B1 [patent_app_number] => 10/002479 [patent_app_country] => US [patent_app_date] => 2001-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2311 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/823/06823487.pdf [firstpage_image] =>[orig_patent_app_number] => 10002479 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/002479
Method and apparatus for enhancing correction power of reverse order error correction codes Nov 14, 2001 Issued
Array ( [id] => 6862736 [patent_doc_number] => 20030093744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-15 [patent_title] => 'Error correcting memory and method of operating same' [patent_app_type] => new [patent_app_number] => 10/003602 [patent_app_country] => US [patent_app_date] => 2001-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9780 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20030093744.pdf [firstpage_image] =>[orig_patent_app_number] => 10003602 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/003602
Error correcting memory and method of operating same Nov 13, 2001 Issued
Array ( [id] => 1144131 [patent_doc_number] => 06785855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Implementation of an assertion check in ATPG models' [patent_app_type] => B2 [patent_app_number] => 10/010797 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4596 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/785/06785855.pdf [firstpage_image] =>[orig_patent_app_number] => 10010797 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/010797
Implementation of an assertion check in ATPG models Nov 12, 2001 Issued
Array ( [id] => 739880 [patent_doc_number] => 07039843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-02 [patent_title] => 'Modeling custom scan flops in level sensitive scan design' [patent_app_type] => utility [patent_app_number] => 10/012130 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3382 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/039/07039843.pdf [firstpage_image] =>[orig_patent_app_number] => 10012130 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/012130
Modeling custom scan flops in level sensitive scan design Nov 12, 2001 Issued
Array ( [id] => 7613787 [patent_doc_number] => 06898744 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-24 [patent_title] => 'Apparatus and methods for monitoring encoder signals' [patent_app_type] => utility [patent_app_number] => 10/001312 [patent_app_country] => US [patent_app_date] => 2001-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5668 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/898/06898744.pdf [firstpage_image] =>[orig_patent_app_number] => 10001312 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/001312
Apparatus and methods for monitoring encoder signals Oct 31, 2001 Issued
Array ( [id] => 6245544 [patent_doc_number] => 20020046381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Out-of-band forward error correction' [patent_app_type] => new [patent_app_number] => 10/016226 [patent_app_country] => US [patent_app_date] => 2001-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 16952 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20020046381.pdf [firstpage_image] =>[orig_patent_app_number] => 10016226 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/016226
Out-of-band forward error correction Oct 31, 2001 Issued
Array ( [id] => 5830547 [patent_doc_number] => 20020069381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Nonvolatile semiconductor memory device with a fail bit detecting scheme and method for counting the number of fail bits' [patent_app_type] => new [patent_app_number] => 10/003390 [patent_app_country] => US [patent_app_date] => 2001-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6394 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20020069381.pdf [firstpage_image] =>[orig_patent_app_number] => 10003390 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/003390
Nonvolatile semiconductor memory device with a fail bit detecting scheme and method for counting the number of fail bits Oct 29, 2001 Issued
Array ( [id] => 1093018 [patent_doc_number] => 06829741 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-07 [patent_title] => 'Forward error correction (FEC) based on SONET/SDH framing' [patent_app_type] => B1 [patent_app_number] => 10/003029 [patent_app_country] => US [patent_app_date] => 2001-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8222 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/829/06829741.pdf [firstpage_image] =>[orig_patent_app_number] => 10003029 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/003029
Forward error correction (FEC) based on SONET/SDH framing Oct 22, 2001 Issued
Array ( [id] => 1218315 [patent_doc_number] => 06711707 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-23 [patent_title] => 'Process of controlling plural test access ports' [patent_app_type] => B2 [patent_app_number] => 09/981514 [patent_app_country] => US [patent_app_date] => 2001-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5784 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711707.pdf [firstpage_image] =>[orig_patent_app_number] => 09981514 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/981514
Process of controlling plural test access ports Oct 15, 2001 Issued
Array ( [id] => 6815072 [patent_doc_number] => 20030074622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'CGROM testing device' [patent_app_type] => new [patent_app_number] => 09/975942 [patent_app_country] => US [patent_app_date] => 2001-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2605 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20030074622.pdf [firstpage_image] =>[orig_patent_app_number] => 09975942 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/975942
CGROM testing device Oct 14, 2001 Issued
Array ( [id] => 6815073 [patent_doc_number] => 20030074623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Algorithmic test pattern generator' [patent_app_type] => new [patent_app_number] => 09/976790 [patent_app_country] => US [patent_app_date] => 2001-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4507 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20030074623.pdf [firstpage_image] =>[orig_patent_app_number] => 09976790 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/976790
Algorithmic test pattern generator Oct 12, 2001 Abandoned
Array ( [id] => 1367104 [patent_doc_number] => 06584595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-24 [patent_title] => 'Technique for correcting single-bit errors in caches with sub-block parity bits' [patent_app_type] => B2 [patent_app_number] => 09/975225 [patent_app_country] => US [patent_app_date] => 2001-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5602 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/584/06584595.pdf [firstpage_image] =>[orig_patent_app_number] => 09975225 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/975225
Technique for correcting single-bit errors in caches with sub-block parity bits Oct 10, 2001 Issued
Array ( [id] => 1129806 [patent_doc_number] => 06795943 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-21 [patent_title] => 'Semiconductor device with test mode' [patent_app_type] => B2 [patent_app_number] => 09/973894 [patent_app_country] => US [patent_app_date] => 2001-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 5953 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/795/06795943.pdf [firstpage_image] =>[orig_patent_app_number] => 09973894 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/973894
Semiconductor device with test mode Oct 10, 2001 Issued
Array ( [id] => 6211691 [patent_doc_number] => 20020073367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Method and integrated circuit for testing a memory having a number of memory banks' [patent_app_type] => new [patent_app_number] => 09/975060 [patent_app_country] => US [patent_app_date] => 2001-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3477 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20020073367.pdf [firstpage_image] =>[orig_patent_app_number] => 09975060 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/975060
Method and integrated circuit for testing a memory having a number of memory banks Oct 10, 2001 Abandoned
Array ( [id] => 6815061 [patent_doc_number] => 20030074611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Efficient test structure for non-volatile memory and other semiconductor integrated circuits' [patent_app_type] => new [patent_app_number] => 09/975064 [patent_app_country] => US [patent_app_date] => 2001-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5622 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20030074611.pdf [firstpage_image] =>[orig_patent_app_number] => 09975064 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/975064
Efficient test structure for non-volatile memory and other semiconductor integrated circuits Oct 9, 2001 Issued
Array ( [id] => 6757599 [patent_doc_number] => 20030005376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'System and method for automatically analyzing and managing loss factors in test process of semiconductor integrated circuit devices' [patent_app_type] => new [patent_app_number] => 09/971934 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5447 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20030005376.pdf [firstpage_image] =>[orig_patent_app_number] => 09971934 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/971934
System and method for automatically analyzing and managing loss factors in test process of semiconductor integrated circuit devices Oct 8, 2001 Issued
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