Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5990891 [patent_doc_number] => 20020099992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'System for reducing test data volume in the testing of logic products' [patent_app_type] => new [patent_app_number] => 09/972000 [patent_app_country] => US [patent_app_date] => 2001-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5797 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20020099992.pdf [firstpage_image] =>[orig_patent_app_number] => 09972000 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/972000
System for reducing test data volume in the testing of logic products Oct 4, 2001 Issued
Array ( [id] => 1602327 [patent_doc_number] => 06493839 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Apparatus and method for testing memory in a microprocessor' [patent_app_type] => B1 [patent_app_number] => 09/970280 [patent_app_country] => US [patent_app_date] => 2001-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8736 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493839.pdf [firstpage_image] =>[orig_patent_app_number] => 09970280 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/970280
Apparatus and method for testing memory in a microprocessor Oct 2, 2001 Issued
Array ( [id] => 7628127 [patent_doc_number] => 06820234 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-16 [patent_title] => 'Skew calibration means and a method of skew calibration' [patent_app_type] => B2 [patent_app_number] => 09/967535 [patent_app_country] => US [patent_app_date] => 2001-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 12851 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 8 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/820/06820234.pdf [firstpage_image] =>[orig_patent_app_number] => 09967535 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/967535
Skew calibration means and a method of skew calibration Sep 30, 2001 Issued
Array ( [id] => 1181518 [patent_doc_number] => 06754866 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Testing of integrated circuit devices' [patent_app_type] => B1 [patent_app_number] => 09/967389 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6788 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754866.pdf [firstpage_image] =>[orig_patent_app_number] => 09967389 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/967389
Testing of integrated circuit devices Sep 27, 2001 Issued
Array ( [id] => 6580573 [patent_doc_number] => 20020041242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-11 [patent_title] => 'Semiconductor apparatus' [patent_app_type] => new [patent_app_number] => 09/964483 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 18158 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20020041242.pdf [firstpage_image] =>[orig_patent_app_number] => 09964483 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/964483
Semiconductor apparatus Sep 27, 2001 Abandoned
Array ( [id] => 5816247 [patent_doc_number] => 20020040455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-04 [patent_title] => 'Semiconductor apparatus for providing reliable data analysys of signals' [patent_app_type] => new [patent_app_number] => 09/965565 [patent_app_country] => US [patent_app_date] => 2001-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8750 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20020040455.pdf [firstpage_image] =>[orig_patent_app_number] => 09965565 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/965565
Semiconductor apparatus for providing reliable data analysis of signals Sep 26, 2001 Issued
Array ( [id] => 6369723 [patent_doc_number] => 20020059547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Semiconductor integrated circuit including a test facilitation circuit for functional blocks intellectual properties and automatic insertion method of the same test facilitation circuit' [patent_app_type] => new [patent_app_number] => 09/960414 [patent_app_country] => US [patent_app_date] => 2001-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7922 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20020059547.pdf [firstpage_image] =>[orig_patent_app_number] => 09960414 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/960414
Semiconductor integrated circuit including a test facilitation circuit for functional blocks intellectual properties and automatic insertion method of the same test facilitation circuit Sep 23, 2001 Issued
Array ( [id] => 786142 [patent_doc_number] => 06993693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-31 [patent_title] => 'Analogue/digital interface circuit' [patent_app_type] => utility [patent_app_number] => 10/363773 [patent_app_country] => US [patent_app_date] => 2001-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1325 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/993/06993693.pdf [firstpage_image] =>[orig_patent_app_number] => 10363773 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/363773
Analogue/digital interface circuit Sep 9, 2001 Issued
Array ( [id] => 6099217 [patent_doc_number] => 20020053057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'Test pattern compression for an integrated circuit test environment' [patent_app_type] => new [patent_app_number] => 09/947160 [patent_app_country] => US [patent_app_date] => 2001-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8074 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20020053057.pdf [firstpage_image] =>[orig_patent_app_number] => 09947160 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/947160
Test pattern compression for an integrated circuit test environment Sep 3, 2001 Issued
Array ( [id] => 1250315 [patent_doc_number] => 06675339 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Single platform electronic tester' [patent_app_type] => B1 [patent_app_number] => 09/935453 [patent_app_country] => US [patent_app_date] => 2001-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 19000 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/675/06675339.pdf [firstpage_image] =>[orig_patent_app_number] => 09935453 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/935453
Single platform electronic tester Aug 21, 2001 Issued
Array ( [id] => 1179462 [patent_doc_number] => 06757856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-29 [patent_title] => 'Apparatus and method for hardware-assisted diagnosis of broken logic-test shift-registers' [patent_app_type] => B2 [patent_app_number] => 09/681955 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3259 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/757/06757856.pdf [firstpage_image] =>[orig_patent_app_number] => 09681955 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/681955
Apparatus and method for hardware-assisted diagnosis of broken logic-test shift-registers Jun 28, 2001 Issued
Array ( [id] => 6757604 [patent_doc_number] => 20030005381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Semiconductor test system having double data rate pin scrambling' [patent_app_type] => new [patent_app_number] => 09/895439 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5415 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20030005381.pdf [firstpage_image] =>[orig_patent_app_number] => 09895439 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/895439
Semiconductor test system having double data rate pin scrambling Jun 28, 2001 Issued
Array ( [id] => 1030686 [patent_doc_number] => 06883127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-19 [patent_title] => 'Comparison circuit and method for verification of scan data' [patent_app_type] => utility [patent_app_number] => 09/895589 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6220 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/883/06883127.pdf [firstpage_image] =>[orig_patent_app_number] => 09895589 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/895589
Comparison circuit and method for verification of scan data Jun 27, 2001 Issued
Array ( [id] => 6757601 [patent_doc_number] => 20030005378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Body bias using scan chains' [patent_app_type] => new [patent_app_number] => 09/894465 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4160 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20030005378.pdf [firstpage_image] =>[orig_patent_app_number] => 09894465 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/894465
Body bias using scan chains Jun 27, 2001 Issued
Array ( [id] => 6336365 [patent_doc_number] => 20020199140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'Method and apparatus for collecting and displaying bit-fail-map information' [patent_app_type] => new [patent_app_number] => 09/891837 [patent_app_country] => US [patent_app_date] => 2001-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3166 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20020199140.pdf [firstpage_image] =>[orig_patent_app_number] => 09891837 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/891837
Method and apparatus for collecting and displaying bit-fail-map information Jun 25, 2001 Issued
Array ( [id] => 1419401 [patent_doc_number] => 06546509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Method and system for adaptive interleaving' [patent_app_type] => B2 [patent_app_number] => 09/884878 [patent_app_country] => US [patent_app_date] => 2001-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5713 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546509.pdf [firstpage_image] =>[orig_patent_app_number] => 09884878 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/884878
Method and system for adaptive interleaving Jun 18, 2001 Issued
Array ( [id] => 1521876 [patent_doc_number] => 06502219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-31 [patent_title] => 'Communication device and method for electronic price label systems' [patent_app_type] => B2 [patent_app_number] => 09/879577 [patent_app_country] => US [patent_app_date] => 2001-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3252 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502219.pdf [firstpage_image] =>[orig_patent_app_number] => 09879577 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/879577
Communication device and method for electronic price label systems Jun 11, 2001 Issued
Array ( [id] => 1567736 [patent_doc_number] => 06363512 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Digital data recording channel' [patent_app_type] => B1 [patent_app_number] => 09/872802 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 11544 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363512.pdf [firstpage_image] =>[orig_patent_app_number] => 09872802 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/872802
Digital data recording channel May 31, 2001 Issued
Array ( [id] => 7962159 [patent_doc_number] => 06681350 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-20 [patent_title] => 'Method and apparatus for testing memory cells for data retention faults' [patent_app_type] => B2 [patent_app_number] => 09/681602 [patent_app_country] => US [patent_app_date] => 2001-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2498 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/681/06681350.pdf [firstpage_image] =>[orig_patent_app_number] => 09681602 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/681602
Method and apparatus for testing memory cells for data retention faults May 4, 2001 Issued
Array ( [id] => 6894564 [patent_doc_number] => 20010016930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'Threefold error correction coding method and apparatus for high definition digital video cassette recorder' [patent_app_type] => new [patent_app_number] => 09/842085 [patent_app_country] => US [patent_app_date] => 2001-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4162 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20010016930.pdf [firstpage_image] =>[orig_patent_app_number] => 09842085 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/842085
Threefold error correction coding method and apparatus for high definition digital video cassette recorder Apr 25, 2001 Issued
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