Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1525037 [patent_doc_number] => 06415412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-02 [patent_title] => 'Signal used in the transmission of data in a communication system' [patent_app_type] => B2 [patent_app_number] => 09/835352 [patent_app_country] => US [patent_app_date] => 2001-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4910 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415412.pdf [firstpage_image] =>[orig_patent_app_number] => 09835352 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/835352
Signal used in the transmission of data in a communication system Apr 16, 2001 Issued
Array ( [id] => 6746735 [patent_doc_number] => 20030023918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Forward error correction techniques' [patent_app_type] => new [patent_app_number] => 09/835361 [patent_app_country] => US [patent_app_date] => 2001-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9094 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20030023918.pdf [firstpage_image] =>[orig_patent_app_number] => 09835361 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/835361
Forward error correction techniques Apr 16, 2001 Issued
Array ( [id] => 1166925 [patent_doc_number] => 06772378 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-03 [patent_title] => 'Dummy error addition circuit' [patent_app_type] => B1 [patent_app_number] => 09/807029 [patent_app_country] => US [patent_app_date] => 2001-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4532 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/772/06772378.pdf [firstpage_image] =>[orig_patent_app_number] => 09807029 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/807029
Dummy error addition circuit Apr 8, 2001 Issued
Array ( [id] => 5816249 [patent_doc_number] => 20020040457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-04 [patent_title] => 'System and method for applying flexible constraints' [patent_app_type] => new [patent_app_number] => 09/823970 [patent_app_country] => US [patent_app_date] => 2001-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6061 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20020040457.pdf [firstpage_image] =>[orig_patent_app_number] => 09823970 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/823970
System and method for applying flexible constraints Apr 2, 2001 Issued
Array ( [id] => 1248981 [patent_doc_number] => 06678862 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Detection apparatus' [patent_app_type] => B1 [patent_app_number] => 09/806585 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 7271 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678862.pdf [firstpage_image] =>[orig_patent_app_number] => 09806585 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/806585
Detection apparatus Mar 29, 2001 Issued
Array ( [id] => 7622297 [patent_doc_number] => 06687869 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Method for evaluating a presentation layer data unit' [patent_app_type] => B1 [patent_app_number] => 09/806429 [patent_app_country] => US [patent_app_date] => 2001-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4312 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687869.pdf [firstpage_image] =>[orig_patent_app_number] => 09806429 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/806429
Method for evaluating a presentation layer data unit Mar 28, 2001 Issued
Array ( [id] => 6922190 [patent_doc_number] => 20010029594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-11 [patent_title] => 'Method and apparatus of pre-loading a seed for a test code of a physical layer device' [patent_app_type] => new [patent_app_number] => 09/814826 [patent_app_country] => US [patent_app_date] => 2001-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20010029594.pdf [firstpage_image] =>[orig_patent_app_number] => 09814826 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/814826
Method and apparatus of pre-loading a seed for a test code of a physical layer device Mar 22, 2001 Issued
Array ( [id] => 6211701 [patent_doc_number] => 20020073376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Data processing method using error-correcting code and an apparatus using the same method' [patent_app_type] => new [patent_app_number] => 09/813782 [patent_app_country] => US [patent_app_date] => 2001-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10373 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 26 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20020073376.pdf [firstpage_image] =>[orig_patent_app_number] => 09813782 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/813782
Data processing method using error-correcting code and an apparatus using the same method Mar 21, 2001 Issued
Array ( [id] => 6461421 [patent_doc_number] => 20020178413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Time data compression technique for high speed integrated circuit memory devices' [patent_app_type] => new [patent_app_number] => 09/815147 [patent_app_country] => US [patent_app_date] => 2001-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4770 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20020178413.pdf [firstpage_image] =>[orig_patent_app_number] => 09815147 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/815147
Time data compression technique for high speed integrated circuit memory devices Mar 21, 2001 Issued
Array ( [id] => 6461496 [patent_doc_number] => 20020178418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Channel coding with unequal error protection for multi-mode source coded information' [patent_app_type] => new [patent_app_number] => 09/814505 [patent_app_country] => US [patent_app_date] => 2001-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6541 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20020178418.pdf [firstpage_image] =>[orig_patent_app_number] => 09814505 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/814505
Channel coding with unequal error protection for multi-mode source coded information Mar 21, 2001 Issued
Array ( [id] => 6510775 [patent_doc_number] => 20020135391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Systems and methods for facilitating testing of pad receivers of integrated circuits' [patent_app_type] => new [patent_app_number] => 09/813752 [patent_app_country] => US [patent_app_date] => 2001-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6780 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20020135391.pdf [firstpage_image] =>[orig_patent_app_number] => 09813752 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/813752
Systems and methods for facilitating testing of pad receivers of integrated circuits Mar 20, 2001 Issued
Array ( [id] => 1186473 [patent_doc_number] => 06742155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-25 [patent_title] => 'System and method for forward error correction' [patent_app_type] => B2 [patent_app_number] => 09/814468 [patent_app_country] => US [patent_app_date] => 2001-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2662 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/742/06742155.pdf [firstpage_image] =>[orig_patent_app_number] => 09814468 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/814468
System and method for forward error correction Mar 20, 2001 Issued
Array ( [id] => 1097513 [patent_doc_number] => 06826722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-30 [patent_title] => 'Method and apparatus for reproducing data and method and apparatus for recording and/or reproducing data' [patent_app_type] => B2 [patent_app_number] => 09/814280 [patent_app_country] => US [patent_app_date] => 2001-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 17777 [patent_no_of_claims] => 92 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826722.pdf [firstpage_image] =>[orig_patent_app_number] => 09814280 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/814280
Method and apparatus for reproducing data and method and apparatus for recording and/or reproducing data Mar 20, 2001 Issued
Array ( [id] => 1258648 [patent_doc_number] => 06671848 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Test circuit for exposing higher order speed paths' [patent_app_type] => B1 [patent_app_number] => 09/813339 [patent_app_country] => US [patent_app_date] => 2001-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4184 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/671/06671848.pdf [firstpage_image] =>[orig_patent_app_number] => 09813339 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/813339
Test circuit for exposing higher order speed paths Mar 19, 2001 Issued
Array ( [id] => 6211698 [patent_doc_number] => 20020073373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Test method of semiconductor intergrated circuit and test pattern generator' [patent_app_type] => new [patent_app_number] => 09/811435 [patent_app_country] => US [patent_app_date] => 2001-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 14837 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20020073373.pdf [firstpage_image] =>[orig_patent_app_number] => 09811435 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/811435
Test method of semiconductor intergrated circuit and test pattern generator Mar 19, 2001 Issued
Array ( [id] => 1177961 [patent_doc_number] => 06760872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-06 [patent_title] => 'Configurable and memory architecture independent memory built-in self test' [patent_app_type] => B2 [patent_app_number] => 09/812109 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5123 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760872.pdf [firstpage_image] =>[orig_patent_app_number] => 09812109 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/812109
Configurable and memory architecture independent memory built-in self test Mar 18, 2001 Issued
Array ( [id] => 1285003 [patent_doc_number] => 06651213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-18 [patent_title] => 'Programmable multi-level track layout method and system for optimizing ECC redundancy in data storage devices' [patent_app_type] => B2 [patent_app_number] => 09/811882 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3505 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/651/06651213.pdf [firstpage_image] =>[orig_patent_app_number] => 09811882 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/811882
Programmable multi-level track layout method and system for optimizing ECC redundancy in data storage devices Mar 18, 2001 Issued
Array ( [id] => 789513 [patent_doc_number] => 06988231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-17 [patent_title] => 'On-chip method and apparatus for testing semiconductor circuits' [patent_app_type] => utility [patent_app_number] => 09/809897 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3121 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/988/06988231.pdf [firstpage_image] =>[orig_patent_app_number] => 09809897 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/809897
On-chip method and apparatus for testing semiconductor circuits Mar 15, 2001 Issued
Array ( [id] => 7611290 [patent_doc_number] => 06904552 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Circuit and method for test and repair' [patent_app_type] => utility [patent_app_number] => 09/810366 [patent_app_country] => US [patent_app_date] => 2001-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3906 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/904/06904552.pdf [firstpage_image] =>[orig_patent_app_number] => 09810366 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/810366
Circuit and method for test and repair Mar 14, 2001 Issued
Array ( [id] => 5848548 [patent_doc_number] => 20020133762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'Method and apparatus for sliding window link physical error detection' [patent_app_type] => new [patent_app_number] => 09/809443 [patent_app_country] => US [patent_app_date] => 2001-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4202 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20020133762.pdf [firstpage_image] =>[orig_patent_app_number] => 09809443 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/809443
Method and apparatus for sliding window link physical error detection Mar 14, 2001 Issued
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