Search

Christine Trinh Le Tu

Examiner (ID: 2588)

Most Active Art Unit
2117
Art Unit(s)
2313, 2133, 2111, 2117, 2784, 2785, 2138, 2413
Total Applications
1748
Issued Applications
1570
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17128445 [patent_doc_number] => 20210303214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => MEMORY SYSTEM AND INFORMATION PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 17/185104 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17185104 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/185104
Memory system and information processing system Feb 24, 2021 Issued
Array ( [id] => 18217550 [patent_doc_number] => 11592481 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-02-28 [patent_title] => Unified approach for improved testing of low power designs with clock gating cells [patent_app_type] => utility [patent_app_number] => 17/182405 [patent_app_country] => US [patent_app_date] => 2021-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17182405 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/182405
Unified approach for improved testing of low power designs with clock gating cells Feb 22, 2021 Issued
Array ( [id] => 17558937 [patent_doc_number] => 11315656 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-26 [patent_title] => Detection circuit and detection method [patent_app_type] => utility [patent_app_number] => 17/182324 [patent_app_country] => US [patent_app_date] => 2021-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3533 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17182324 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/182324
Detection circuit and detection method Feb 22, 2021 Issued
Array ( [id] => 16873311 [patent_doc_number] => 20210166778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => CHIP TESTING METHOD, DEVICE, ELECTRONIC APPARATUS AND COMPUTER READABLE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/176536 [patent_app_country] => US [patent_app_date] => 2021-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6076 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17176536 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/176536
Chip testing method, device, electronic apparatus and computer readable medium Feb 15, 2021 Issued
Array ( [id] => 16872246 [patent_doc_number] => 20210165713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/174399 [patent_app_country] => US [patent_app_date] => 2021-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17886 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17174399 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/174399
Memory system Feb 11, 2021 Issued
Array ( [id] => 18607856 [patent_doc_number] => 11749332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Effective DRAM interleaving for asymmetric size channels or ranks while supporting improved partial array self-refresh [patent_app_type] => utility [patent_app_number] => 17/174073 [patent_app_country] => US [patent_app_date] => 2021-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 19266 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17174073 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/174073
Effective DRAM interleaving for asymmetric size channels or ranks while supporting improved partial array self-refresh Feb 10, 2021 Issued
Array ( [id] => 17607803 [patent_doc_number] => 11336298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Error correction bit flipping scheme [patent_app_type] => utility [patent_app_number] => 17/170259 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14247 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17170259 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/170259
Error correction bit flipping scheme Feb 7, 2021 Issued
Array ( [id] => 17128659 [patent_doc_number] => 20210303428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => ERROR RATE MEASURING APPARATUS AND ERROR COUNTING METHOD [patent_app_type] => utility [patent_app_number] => 17/168581 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8766 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168581 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/168581
Error rate measuring apparatus and error counting method Feb 4, 2021 Issued
Array ( [id] => 17463469 [patent_doc_number] => 20220076775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => TEST CIRCUIT AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE TEST CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/160686 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17160686 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/160686
Test circuit and semiconductor memory system including the test circuit Jan 27, 2021 Issued
Array ( [id] => 17591386 [patent_doc_number] => 11329672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Parallel bit interleaver [patent_app_type] => utility [patent_app_number] => 17/144275 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 35 [patent_no_of_words] => 11041 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17144275 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/144275
Parallel bit interleaver Jan 7, 2021 Issued
Array ( [id] => 17439760 [patent_doc_number] => 11265106 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-01 [patent_title] => Streaming-friendly technology for detection of data [patent_app_type] => utility [patent_app_number] => 17/137340 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5693 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137340 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137340
Streaming-friendly technology for detection of data Dec 28, 2020 Issued
Array ( [id] => 16764230 [patent_doc_number] => 20210109811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => ADAPTIVE DATA AND PARITY PLACEMENT USING COMPRESSION RATIOS OF STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 17/247743 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9885 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17247743 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/247743
Adaptive data and parity placement using compression ratios of storage devices Dec 20, 2020 Issued
Array ( [id] => 18548052 [patent_doc_number] => 11721410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Glitch detection in microelectronic devices, and related devices, systems, and methods [patent_app_type] => utility [patent_app_number] => 17/129596 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 11293 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17129596 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/129596
Glitch detection in microelectronic devices, and related devices, systems, and methods Dec 20, 2020 Issued
Array ( [id] => 17510087 [patent_doc_number] => 20220103191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => MASKED FAULT DETECTION FOR RELIABLE LOW VOLTAGE CACHE OPERATION [patent_app_type] => utility [patent_app_number] => 17/125145 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8022 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125145 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/125145
Masked fault detection for reliable low voltage cache operation Dec 16, 2020 Issued
Array ( [id] => 17659269 [patent_doc_number] => 20220179734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => DATA RECOVERY SYSTEM FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/116969 [patent_app_country] => US [patent_app_date] => 2020-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11888 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17116969 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/116969
Data recovery system for memory devices Dec 8, 2020 Issued
Array ( [id] => 17846712 [patent_doc_number] => 11436085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Dynamic over provisioning allocation for purposed blocks [patent_app_type] => utility [patent_app_number] => 17/112786 [patent_app_country] => US [patent_app_date] => 2020-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13825 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17112786 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/112786
Dynamic over provisioning allocation for purposed blocks Dec 3, 2020 Issued
Array ( [id] => 17308379 [patent_doc_number] => 11209482 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-12-28 [patent_title] => Methods and devices for testing comparators [patent_app_type] => utility [patent_app_number] => 17/107370 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13653 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107370 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107370
Methods and devices for testing comparators Nov 29, 2020 Issued
Array ( [id] => 16716545 [patent_doc_number] => 20210083692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => PARALLEL BIT INTERLEAVER [patent_app_type] => utility [patent_app_number] => 17/102739 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17102739 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/102739
Parallel bit interleaver Nov 23, 2020 Issued
Array ( [id] => 17515617 [patent_doc_number] => 11294767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Deferred error-correction parity calculations [patent_app_type] => utility [patent_app_number] => 17/100622 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11527 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17100622 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/100622
Deferred error-correction parity calculations Nov 19, 2020 Issued
Array ( [id] => 16848233 [patent_doc_number] => 20210148978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => JOINT TEST ACTION GROUP TRANSMISSION SYSTEM CAPABLE OF TRANSMITTING DATA CONTINUOUSLY [patent_app_type] => utility [patent_app_number] => 17/094770 [patent_app_country] => US [patent_app_date] => 2020-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094770 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/094770
Joint test action group transmission system capable of transmitting data continuously Nov 9, 2020 Issued
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