Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1573879 [patent_doc_number] => 06499125 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Method for inserting test circuit and method for converting test data' [patent_app_type] => B1 [patent_app_number] => 09/447677 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12245 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/499/06499125.pdf [firstpage_image] =>[orig_patent_app_number] => 09447677 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/447677
Method for inserting test circuit and method for converting test data Nov 22, 1999 Issued
Array ( [id] => 1417513 [patent_doc_number] => 06532565 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Burst error and additional random bit error correction in a memory' [patent_app_type] => B1 [patent_app_number] => 09/440323 [patent_app_country] => US [patent_app_date] => 1999-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4459 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/532/06532565.pdf [firstpage_image] =>[orig_patent_app_number] => 09440323 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/440323
Burst error and additional random bit error correction in a memory Nov 14, 1999 Issued
Array ( [id] => 1410219 [patent_doc_number] => 06557128 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Semiconductor test system supporting multiple virtual logic testers' [patent_app_type] => B1 [patent_app_number] => 09/439864 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 6466 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557128.pdf [firstpage_image] =>[orig_patent_app_number] => 09439864 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439864
Semiconductor test system supporting multiple virtual logic testers Nov 11, 1999 Issued
Array ( [id] => 1425675 [patent_doc_number] => 06536006 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Event tester architecture for mixed signal testing' [patent_app_type] => B1 [patent_app_number] => 09/439865 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6601 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/536/06536006.pdf [firstpage_image] =>[orig_patent_app_number] => 09439865 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439865
Event tester architecture for mixed signal testing Nov 11, 1999 Issued
Array ( [id] => 950209 [patent_doc_number] => 06964008 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-08 [patent_title] => 'Data checksum method and apparatus' [patent_app_type] => utility [patent_app_number] => 09/439776 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 11961 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/964/06964008.pdf [firstpage_image] =>[orig_patent_app_number] => 09439776 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439776
Data checksum method and apparatus Nov 11, 1999 Issued
Array ( [id] => 7645853 [patent_doc_number] => 06477670 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Data link layer quality of service for UMTS' [patent_app_type] => B1 [patent_app_number] => 09/432567 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3902 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477670.pdf [firstpage_image] =>[orig_patent_app_number] => 09432567 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/432567
Data link layer quality of service for UMTS Nov 11, 1999 Issued
Array ( [id] => 1429752 [patent_doc_number] => 06530055 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Method and apparatus for receiving and decoding coded information, including transfer of error information from transmission layer to coding layer' [patent_app_type] => B1 [patent_app_number] => 09/439497 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 26 [patent_no_of_words] => 12712 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/530/06530055.pdf [firstpage_image] =>[orig_patent_app_number] => 09439497 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439497
Method and apparatus for receiving and decoding coded information, including transfer of error information from transmission layer to coding layer Nov 11, 1999 Issued
Array ( [id] => 1424062 [patent_doc_number] => 06539511 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Semiconductor integrated circuit devices with test circuit' [patent_app_type] => B1 [patent_app_number] => 09/438541 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 53 [patent_no_of_words] => 24099 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539511.pdf [firstpage_image] =>[orig_patent_app_number] => 09438541 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/438541
Semiconductor integrated circuit devices with test circuit Nov 11, 1999 Issued
Array ( [id] => 1431454 [patent_doc_number] => 06523147 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Method and apparatus for forward error correction coding for an AM in-band on-channel digital audio broadcasting system' [patent_app_type] => B1 [patent_app_number] => 09/438822 [patent_app_country] => US [patent_app_date] => 1999-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8808 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/523/06523147.pdf [firstpage_image] =>[orig_patent_app_number] => 09438822 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/438822
Method and apparatus for forward error correction coding for an AM in-band on-channel digital audio broadcasting system Nov 10, 1999 Issued
Array ( [id] => 7644097 [patent_doc_number] => 06473877 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'ECC code mechanism to detect wire stuck-at faults' [patent_app_type] => B1 [patent_app_number] => 09/438063 [patent_app_country] => US [patent_app_date] => 1999-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 4852 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/473/06473877.pdf [firstpage_image] =>[orig_patent_app_number] => 09438063 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/438063
ECC code mechanism to detect wire stuck-at faults Nov 9, 1999 Issued
Array ( [id] => 1424023 [patent_doc_number] => 06539507 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Integrated circuit with alternately selectable state evaluation provisions' [patent_app_type] => B1 [patent_app_number] => 09/437813 [patent_app_country] => US [patent_app_date] => 1999-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4917 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539507.pdf [firstpage_image] =>[orig_patent_app_number] => 09437813 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/437813
Integrated circuit with alternately selectable state evaluation provisions Nov 9, 1999 Issued
Array ( [id] => 1407897 [patent_doc_number] => 06560747 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Error counting mechanism' [patent_app_type] => B1 [patent_app_number] => 09/437696 [patent_app_country] => US [patent_app_date] => 1999-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7122 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560747.pdf [firstpage_image] =>[orig_patent_app_number] => 09437696 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/437696
Error counting mechanism Nov 9, 1999 Issued
Array ( [id] => 1410353 [patent_doc_number] => 06557136 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Method and system for limiting the maximum number of consecutive zeroes in a block for communications or storage' [patent_app_type] => B1 [patent_app_number] => 09/437698 [patent_app_country] => US [patent_app_date] => 1999-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3689 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557136.pdf [firstpage_image] =>[orig_patent_app_number] => 09437698 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/437698
Method and system for limiting the maximum number of consecutive zeroes in a block for communications or storage Nov 9, 1999 Issued
Array ( [id] => 1396335 [patent_doc_number] => 06567940 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Method of testing random-access memory' [patent_app_type] => B1 [patent_app_number] => 09/437409 [patent_app_country] => US [patent_app_date] => 1999-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1646 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567940.pdf [firstpage_image] =>[orig_patent_app_number] => 09437409 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/437409
Method of testing random-access memory Nov 9, 1999 Issued
Array ( [id] => 7625684 [patent_doc_number] => 06769083 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-27 [patent_title] => 'Test pattern generator, a testing device, and a method of generating a plurality of test patterns' [patent_app_type] => B1 [patent_app_number] => 09/437249 [patent_app_country] => US [patent_app_date] => 1999-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 26 [patent_no_of_words] => 14099 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/769/06769083.pdf [firstpage_image] =>[orig_patent_app_number] => 09437249 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/437249
Test pattern generator, a testing device, and a method of generating a plurality of test patterns Nov 9, 1999 Issued
Array ( [id] => 1567683 [patent_doc_number] => 06438717 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'High speed parallel bit error rate tester' [patent_app_type] => B1 [patent_app_number] => 09/436350 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1803 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438717.pdf [firstpage_image] =>[orig_patent_app_number] => 09436350 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/436350
High speed parallel bit error rate tester Nov 8, 1999 Issued
Array ( [id] => 1431447 [patent_doc_number] => 06523145 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Method and apparatus for testing a contents-addressable-memory-type structure using a simultaneous write-thru mode' [patent_app_type] => B1 [patent_app_number] => 09/435877 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4184 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/523/06523145.pdf [firstpage_image] =>[orig_patent_app_number] => 09435877 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/435877
Method and apparatus for testing a contents-addressable-memory-type structure using a simultaneous write-thru mode Nov 7, 1999 Issued
Array ( [id] => 7638558 [patent_doc_number] => 06397363 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Semiconductor integrated circuit device with test circuit' [patent_app_type] => B1 [patent_app_number] => 09/435622 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 7730 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397363.pdf [firstpage_image] =>[orig_patent_app_number] => 09435622 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/435622
Semiconductor integrated circuit device with test circuit Nov 7, 1999 Issued
Array ( [id] => 1412587 [patent_doc_number] => 06553526 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Programmable array built-in self test method and system for arrays with imbedded logic' [patent_app_type] => B1 [patent_app_number] => 09/435873 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4320 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553526.pdf [firstpage_image] =>[orig_patent_app_number] => 09435873 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/435873
Programmable array built-in self test method and system for arrays with imbedded logic Nov 7, 1999 Issued
Array ( [id] => 1170628 [patent_doc_number] => 06766489 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-20 [patent_title] => 'Device and method of adapting turbocoders and the associated decoders to sequences of variable length' [patent_app_type] => B1 [patent_app_number] => 09/435351 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11662 [patent_no_of_claims] => 80 [patent_no_of_ind_claims] => 54 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766489.pdf [firstpage_image] =>[orig_patent_app_number] => 09435351 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/435351
Device and method of adapting turbocoders and the associated decoders to sequences of variable length Nov 7, 1999 Issued
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