Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1567717 [patent_doc_number] => 06363508 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Method for testing reflection LCD projector and display panel pixel area thereof' [patent_app_type] => B1 [patent_app_number] => 09/436689 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9986 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363508.pdf [firstpage_image] =>[orig_patent_app_number] => 09436689 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/436689
Method for testing reflection LCD projector and display panel pixel area thereof Nov 7, 1999 Issued
Array ( [id] => 1412602 [patent_doc_number] => 06553527 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Programmable array built-in self test method and controller with programmable expect generator' [patent_app_type] => B1 [patent_app_number] => 09/435875 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3927 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553527.pdf [firstpage_image] =>[orig_patent_app_number] => 09435875 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/435875
Programmable array built-in self test method and controller with programmable expect generator Nov 7, 1999 Issued
Array ( [id] => 1396388 [patent_doc_number] => 06567942 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Method and apparatus to reduce the size of programmable array built-in self-test engines' [patent_app_type] => B1 [patent_app_number] => 09/435874 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3431 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567942.pdf [firstpage_image] =>[orig_patent_app_number] => 09435874 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/435874
Method and apparatus to reduce the size of programmable array built-in self-test engines Nov 7, 1999 Issued
Array ( [id] => 1412570 [patent_doc_number] => 06553525 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Method and apparatus for selectively enabling and disabling functions on a per array basis' [patent_app_type] => B1 [patent_app_number] => 09/435870 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5589 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553525.pdf [firstpage_image] =>[orig_patent_app_number] => 09435870 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/435870
Method and apparatus for selectively enabling and disabling functions on a per array basis Nov 7, 1999 Issued
Array ( [id] => 1402004 [patent_doc_number] => 06564344 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'System and method of generating dynamic word line from the content addressable memory (CAM) hit/miss signal which is scannable for testability' [patent_app_type] => B1 [patent_app_number] => 09/435866 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4328 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564344.pdf [firstpage_image] =>[orig_patent_app_number] => 09435866 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/435866
System and method of generating dynamic word line from the content addressable memory (CAM) hit/miss signal which is scannable for testability Nov 7, 1999 Issued
Array ( [id] => 1281595 [patent_doc_number] => 06638318 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-28 [patent_title] => 'Method and device for coding sequences of data, and associated decoding method and device' [patent_app_type] => B1 [patent_app_number] => 09/434402 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4739 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/638/06638318.pdf [firstpage_image] =>[orig_patent_app_number] => 09434402 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/434402
Method and device for coding sequences of data, and associated decoding method and device Nov 4, 1999 Issued
Array ( [id] => 1456945 [patent_doc_number] => 06457150 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method and apparatus for on-chip monitoring of integrated circuits with a distributed system' [patent_app_type] => B1 [patent_app_number] => 09/433233 [patent_app_country] => US [patent_app_date] => 1999-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3137 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457150.pdf [firstpage_image] =>[orig_patent_app_number] => 09433233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/433233
Method and apparatus for on-chip monitoring of integrated circuits with a distributed system Nov 3, 1999 Issued
Array ( [id] => 1525000 [patent_doc_number] => 06415400 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Method of managing defect areas on an erasable optical disc in a dynamic manner' [patent_app_type] => B1 [patent_app_number] => 09/434863 [patent_app_country] => US [patent_app_date] => 1999-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4832 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 447 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415400.pdf [firstpage_image] =>[orig_patent_app_number] => 09434863 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/434863
Method of managing defect areas on an erasable optical disc in a dynamic manner Nov 3, 1999 Issued
Array ( [id] => 1421726 [patent_doc_number] => 06543016 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Testing content-addressable memories' [patent_app_type] => B1 [patent_app_number] => 09/433759 [patent_app_country] => US [patent_app_date] => 1999-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 6 [patent_no_of_words] => 7325 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/543/06543016.pdf [firstpage_image] =>[orig_patent_app_number] => 09433759 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/433759
Testing content-addressable memories Nov 3, 1999 Issued
Array ( [id] => 1402078 [patent_doc_number] => 06564348 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Method and apparatus for storing and using chipset built-in self-test signatures' [patent_app_type] => B1 [patent_app_number] => 09/434874 [patent_app_country] => US [patent_app_date] => 1999-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2600 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564348.pdf [firstpage_image] =>[orig_patent_app_number] => 09434874 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/434874
Method and apparatus for storing and using chipset built-in self-test signatures Nov 3, 1999 Issued
Array ( [id] => 1430641 [patent_doc_number] => 06526532 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Channel error correction apparatus and method' [patent_app_type] => B1 [patent_app_number] => 09/434319 [patent_app_country] => US [patent_app_date] => 1999-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 6495 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/526/06526532.pdf [firstpage_image] =>[orig_patent_app_number] => 09434319 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/434319
Channel error correction apparatus and method Nov 3, 1999 Issued
Array ( [id] => 1462540 [patent_doc_number] => 06427220 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Method and apparatus for prml detection incorporating a cyclic code' [patent_app_type] => B1 [patent_app_number] => 09/434207 [patent_app_country] => US [patent_app_date] => 1999-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4668 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/427/06427220.pdf [firstpage_image] =>[orig_patent_app_number] => 09434207 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/434207
Method and apparatus for prml detection incorporating a cyclic code Nov 3, 1999 Issued
Array ( [id] => 7645847 [patent_doc_number] => 06477676 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Intermediate stage of a multi-stage algorithmic pattern generator for testing IC chips' [patent_app_type] => B1 [patent_app_number] => 09/432968 [patent_app_country] => US [patent_app_date] => 1999-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 36 [patent_no_of_words] => 27757 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477676.pdf [firstpage_image] =>[orig_patent_app_number] => 09432968 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/432968
Intermediate stage of a multi-stage algorithmic pattern generator for testing IC chips Nov 2, 1999 Issued
Array ( [id] => 1533322 [patent_doc_number] => 06480981 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Output stage of a multi-stage algorithmic pattern generator for testing IC chips' [patent_app_type] => B1 [patent_app_number] => 09/432967 [patent_app_country] => US [patent_app_date] => 1999-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 36 [patent_no_of_words] => 27803 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480981.pdf [firstpage_image] =>[orig_patent_app_number] => 09432967 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/432967
Output stage of a multi-stage algorithmic pattern generator for testing IC chips Nov 2, 1999 Issued
Array ( [id] => 1525026 [patent_doc_number] => 06415408 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Multi-stage algorithmic pattern generator for testing IC chips' [patent_app_type] => B1 [patent_app_number] => 09/432965 [patent_app_country] => US [patent_app_date] => 1999-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 36 [patent_no_of_words] => 27759 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415408.pdf [firstpage_image] =>[orig_patent_app_number] => 09432965 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/432965
Multi-stage algorithmic pattern generator for testing IC chips Nov 2, 1999 Issued
Array ( [id] => 1525031 [patent_doc_number] => 06415409 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'System for testing IC chips selectively with stored or internally generated bit streams' [patent_app_type] => B1 [patent_app_number] => 09/432966 [patent_app_country] => US [patent_app_date] => 1999-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 36 [patent_no_of_words] => 27705 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415409.pdf [firstpage_image] =>[orig_patent_app_number] => 09432966 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/432966
System for testing IC chips selectively with stored or internally generated bit streams Nov 2, 1999 Issued
Array ( [id] => 1602329 [patent_doc_number] => 06493840 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Testability architecture for modularized integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/433611 [patent_app_country] => US [patent_app_date] => 1999-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3052 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493840.pdf [firstpage_image] =>[orig_patent_app_number] => 09433611 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/433611
Testability architecture for modularized integrated circuits Nov 1, 1999 Issued
Array ( [id] => 1429364 [patent_doc_number] => 06513136 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'Communications receiver arrangement' [patent_app_type] => B1 [patent_app_number] => 09/432317 [patent_app_country] => US [patent_app_date] => 1999-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2575 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/513/06513136.pdf [firstpage_image] =>[orig_patent_app_number] => 09432317 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/432317
Communications receiver arrangement Nov 1, 1999 Issued
Array ( [id] => 1424013 [patent_doc_number] => 06539506 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Read/write memory with self-test device and associated test method' [patent_app_type] => B1 [patent_app_number] => 09/431529 [patent_app_country] => US [patent_app_date] => 1999-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5629 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539506.pdf [firstpage_image] =>[orig_patent_app_number] => 09431529 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/431529
Read/write memory with self-test device and associated test method Oct 31, 1999 Issued
Array ( [id] => 1452512 [patent_doc_number] => 06370672 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Determining the received data rate in a variable rate communications system' [patent_app_type] => B1 [patent_app_number] => 09/430994 [patent_app_country] => US [patent_app_date] => 1999-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4743 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370672.pdf [firstpage_image] =>[orig_patent_app_number] => 09430994 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/430994
Determining the received data rate in a variable rate communications system Oct 31, 1999 Issued
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