Christine Trinh Le Tu

Array ( [id] => 4310951 [patent_doc_number] => 06212656 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Automated scan chain sizing using Synopsys' [patent_app_type] => 1 [patent_app_number] => 9/208594 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4828 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212656.pdf [firstpage_image] =>[orig_patent_app_number] => 208594 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4291040 [patent_doc_number] => 06308292 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'File driven mask insertion for automatic test equipment test pattern generation' [patent_app_type] => 1 [patent_app_number] => 9/207191 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6128 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/308/06308292.pdf [firstpage_image] =>[orig_patent_app_number] => 207191 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4124746 [patent_doc_number] => 06101627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Information processing system and logic LSI, detecting a fault in the system or the LSI, by using internal data processed in each of them' [patent_app_type] => 1 [patent_app_number] => 9/206153 [patent_app_country] => US [patent_app_date] => 1998-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 12955 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101627.pdf [firstpage_image] =>[orig_patent_app_number] => 206153 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4382013 [patent_doc_number] => 06256756 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Embedded memory bank system' [patent_app_type] => 1 [patent_app_number] => 9/205489 [patent_app_country] => US [patent_app_date] => 1998-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2461 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256756.pdf [firstpage_image] =>[orig_patent_app_number] => 205489 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4350425 [patent_doc_number] => 06321355 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Semiconductor integrated circuit and method of testing the same' [patent_app_type] => 1 [patent_app_number] => 9/204153 [patent_app_country] => US [patent_app_date] => 1998-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3317 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321355.pdf [firstpage_image] =>[orig_patent_app_number] => 204153 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4318525 [patent_doc_number] => 06185708 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Maintenance free test system' [patent_app_type] => 1 [patent_app_number] => 9/200909 [patent_app_country] => US [patent_app_date] => 1998-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4233 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185708.pdf [firstpage_image] =>[orig_patent_app_number] => 200909 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4382067 [patent_doc_number] => 06256760 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Automatic test equipment scan test enhancement' [patent_app_type] => 1 [patent_app_number] => 9/190292 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6825 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256760.pdf [firstpage_image] =>[orig_patent_app_number] => 190292 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4426998 [patent_doc_number] => 06195776 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Method and system for transforming scan-based sequential circuits with multiple skewed capture events into combinational circuits for more efficient automatic test pattern generation' [patent_app_type] => 1 [patent_app_number] => 9/184518 [patent_app_country] => US [patent_app_date] => 1998-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 17 [patent_no_of_words] => 10041 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195776.pdf [firstpage_image] =>[orig_patent_app_number] => 184518 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1585053 [patent_doc_number] => 06449741 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Single platform electronic tester' [patent_app_type] => B1 [patent_app_number] => 09/183038 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 18966 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449741.pdf [firstpage_image] =>[orig_patent_app_number] => 09183038 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4318632 [patent_doc_number] => 06185715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Method of product code block encoding applicable to encoding an ATM cell' [patent_app_type] => 1 [patent_app_number] => 9/166234 [patent_app_country] => US [patent_app_date] => 1998-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2208 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185715.pdf [firstpage_image] =>[orig_patent_app_number] => 166234 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4403015 [patent_doc_number] => 06279133 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method and apparatus for significantly improving the reliability of multilevel memory architecture' [patent_app_type] => 1 [patent_app_number] => 9/166500 [patent_app_country] => US [patent_app_date] => 1998-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6196 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279133.pdf [firstpage_image] =>[orig_patent_app_number] => 166500 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4380345 [patent_doc_number] => 06192498 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'System and method for generating error checking data in a communications system' [patent_app_type] => 1 [patent_app_number] => 9/164921 [patent_app_country] => US [patent_app_date] => 1998-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8322 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/192/06192498.pdf [firstpage_image] =>[orig_patent_app_number] => 164921 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4374749 [patent_doc_number] => 06175942 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Variable bit width cache memory architecture' [patent_app_type] => 1 [patent_app_number] => 9/161899 [patent_app_country] => US [patent_app_date] => 1998-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3701 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175942.pdf [firstpage_image] =>[orig_patent_app_number] => 161899 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4318874 [patent_doc_number] => 06182255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'IC tester' [patent_app_type] => 1 [patent_app_number] => 9/157016 [patent_app_country] => US [patent_app_date] => 1998-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8716 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/182/06182255.pdf [firstpage_image] =>[orig_patent_app_number] => 157016 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4127445 [patent_doc_number] => 06058502 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Diagnostic system analyzing frequency spectrum of electric power for diagnosing integrated circuit, method and information storage medium storing computer program for the method' [patent_app_type] => 1 [patent_app_number] => 9/145236 [patent_app_country] => US [patent_app_date] => 1998-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 5664 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058502.pdf [firstpage_image] =>[orig_patent_app_number] => 145236 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4110814 [patent_doc_number] => 06134682 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Testable bus control logic circuitry and method for using same' [patent_app_type] => 1 [patent_app_number] => 9/143886 [patent_app_country] => US [patent_app_date] => 1998-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6427 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134682.pdf [firstpage_image] =>[orig_patent_app_number] => 143886 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4423105 [patent_doc_number] => 06272660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Screening for errors in data transmission systems' [patent_app_type] => 1 [patent_app_number] => 9/143911 [patent_app_country] => US [patent_app_date] => 1998-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7451 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272660.pdf [firstpage_image] =>[orig_patent_app_number] => 143911 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4156700 [patent_doc_number] => 06122760 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Burn in technique for chips containing different types of IC circuitry' [patent_app_type] => 1 [patent_app_number] => 9/138997 [patent_app_country] => US [patent_app_date] => 1998-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2454 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122760.pdf [firstpage_image] =>[orig_patent_app_number] => 138997 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4258464 [patent_doc_number] => 06145114 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Method of enhanced max-log-a posteriori probability processing' [patent_app_type] => 1 [patent_app_number] => 9/134151 [patent_app_country] => US [patent_app_date] => 1998-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6698 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145114.pdf [firstpage_image] =>[orig_patent_app_number] => 134151 [rel_patent_id] =>[rel_patent_doc_number] =>)