Christine Trinh Le Tu

Array ( [id] => 4172021 [patent_doc_number] => 06125463 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Integrated circuit with serial test interface and logic for loading a functional register using said interface' [patent_app_type] => 1 [patent_app_number] => 9/093276 [patent_app_country] => US [patent_app_date] => 1998-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3192 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125463.pdf [firstpage_image] =>[orig_patent_app_number] => 093276 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4423778 [patent_doc_number] => 06311303 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Monitor port with selectable trace support' [patent_app_type] => 1 [patent_app_number] => 9/089278 [patent_app_country] => US [patent_app_date] => 1998-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3760 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311303.pdf [firstpage_image] =>[orig_patent_app_number] => 089278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4058180 [patent_doc_number] => 05996098 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Memory tester' [patent_app_type] => 1 [patent_app_number] => 9/077397 [patent_app_country] => US [patent_app_date] => 1998-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3724 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 384 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996098.pdf [firstpage_image] =>[orig_patent_app_number] => 077397 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4427013 [patent_doc_number] => 06195784 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Circuit for detecting reception errors in an asynchronous transmission' [patent_app_type] => 1 [patent_app_number] => 9/082927 [patent_app_country] => US [patent_app_date] => 1998-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2484 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195784.pdf [firstpage_image] =>[orig_patent_app_number] => 082927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4116773 [patent_doc_number] => 06067646 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Method and system for adaptive interleaving' [patent_app_type] => 1 [patent_app_number] => 9/062293 [patent_app_country] => US [patent_app_date] => 1998-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5665 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/067/06067646.pdf [firstpage_image] =>[orig_patent_app_number] => 062293 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4085930 [patent_doc_number] => 06009544 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Deinterleaver' [patent_app_type] => 1 [patent_app_number] => 9/060778 [patent_app_country] => US [patent_app_date] => 1998-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5849 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009544.pdf [firstpage_image] =>[orig_patent_app_number] => 060778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4204291 [patent_doc_number] => 06161210 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'List Viterbi algorithms for tailbiting convolutional codes' [patent_app_type] => 1 [patent_app_number] => 9/054676 [patent_app_country] => US [patent_app_date] => 1998-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 9998 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/161/06161210.pdf [firstpage_image] =>[orig_patent_app_number] => 054676 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4177945 [patent_doc_number] => 06105158 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Screening for undetected errors in data transmission systems' [patent_app_type] => 1 [patent_app_number] => 9/054677 [patent_app_country] => US [patent_app_date] => 1998-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 9869 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/105/06105158.pdf [firstpage_image] =>[orig_patent_app_number] => 054677 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4101343 [patent_doc_number] => 06018816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Information processing system and method, image processing system and method, information processing apparatus and computer readable memory' [patent_app_type] => 1 [patent_app_number] => 9/053747 [patent_app_country] => US [patent_app_date] => 1998-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 56 [patent_no_of_words] => 20818 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018816.pdf [firstpage_image] =>[orig_patent_app_number] => 053747 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4424775 [patent_doc_number] => 06266790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Bit error measurement circuit' [patent_app_type] => 1 [patent_app_number] => 9/050426 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 17753 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 409 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266790.pdf [firstpage_image] =>[orig_patent_app_number] => 050426 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4195294 [patent_doc_number] => 06027243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Parity check circuit' [patent_app_type] => 1 [patent_app_number] => 9/048227 [patent_app_country] => US [patent_app_date] => 1998-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2353 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/027/06027243.pdf [firstpage_image] =>[orig_patent_app_number] => 048227 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4255860 [patent_doc_number] => 06119258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Video error/distortion checker' [patent_app_type] => 1 [patent_app_number] => 9/047979 [patent_app_country] => US [patent_app_date] => 1998-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1254 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119258.pdf [firstpage_image] =>[orig_patent_app_number] => 047979 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4139502 [patent_doc_number] => 06073260 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/038748 [patent_app_country] => US [patent_app_date] => 1998-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5212 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073260.pdf [firstpage_image] =>[orig_patent_app_number] => 038748 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4139464 [patent_doc_number] => 06073258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Method and device for performing two dimensional redundancy calculations on embedded memories avoiding fail data collection' [patent_app_type] => 1 [patent_app_number] => 9/032451 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5699 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073258.pdf [firstpage_image] =>[orig_patent_app_number] => 032451 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4152626 [patent_doc_number] => 06035431 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Semiconductor integrated circuit with test device' [patent_app_type] => 1 [patent_app_number] => 9/030950 [patent_app_country] => US [patent_app_date] => 1998-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5449 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035431.pdf [firstpage_image] =>[orig_patent_app_number] => 030950 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4011905 [patent_doc_number] => 05923681 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Parallel synchronous header correction machine for ATM' [patent_app_type] => 1 [patent_app_number] => 9/028717 [patent_app_country] => US [patent_app_date] => 1998-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2812 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923681.pdf [firstpage_image] =>[orig_patent_app_number] => 028717 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4163021 [patent_doc_number] => 06032277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Method and apparatus for logic testing an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/026530 [patent_app_country] => US [patent_app_date] => 1998-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 9549 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/032/06032277.pdf [firstpage_image] =>[orig_patent_app_number] => 026530 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4261016 [patent_doc_number] => 06167540 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Semiconductor memory device and redundant address selection method therefor' [patent_app_type] => 1 [patent_app_number] => 9/020571 [patent_app_country] => US [patent_app_date] => 1998-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4041 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 450 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/167/06167540.pdf [firstpage_image] =>[orig_patent_app_number] => 020571 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3971297 [patent_doc_number] => 05991906 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Semiconductor integrated circuit device and its test method' [patent_app_type] => 1 [patent_app_number] => 9/009257 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6213 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991906.pdf [firstpage_image] =>[orig_patent_app_number] => 009257 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4055249 [patent_doc_number] => 05909454 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Intermediate rate applications of punctured convolutional codes for 8PSK trellis modulation over satellite channels' [patent_app_type] => 1 [patent_app_number] => 9/008976 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3308 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909454.pdf [firstpage_image] =>[orig_patent_app_number] => 008976 [rel_patent_id] =>[rel_patent_doc_number] =>)