Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4006282 [patent_doc_number] => 05920579 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Digital signal reproduction apparatus' [patent_app_type] => 1 [patent_app_number] => 9/008906 [patent_app_country] => US [patent_app_date] => 1998-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4494 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 367 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920579.pdf [firstpage_image] =>[orig_patent_app_number] => 008906 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/008906
Digital signal reproduction apparatus Jan 15, 1998 Issued
Array ( [id] => 4202912 [patent_doc_number] => 06094741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Viterbi decoding apparatus, method for controlling slip state of convolutional code in viterbi decoding apparatus, and slip state control apparatus' [patent_app_type] => 1 [patent_app_number] => 9/001808 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 7893 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094741.pdf [firstpage_image] =>[orig_patent_app_number] => 001808 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001808
Viterbi decoding apparatus, method for controlling slip state of convolutional code in viterbi decoding apparatus, and slip state control apparatus Dec 30, 1997 Issued
Array ( [id] => 4152703 [patent_doc_number] => 06035437 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Communication device and method for electronic price label systems' [patent_app_type] => 1 [patent_app_number] => 8/992667 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3108 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035437.pdf [firstpage_image] =>[orig_patent_app_number] => 992667 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992667
Communication device and method for electronic price label systems Dec 16, 1997 Issued
Array ( [id] => 4116885 [patent_doc_number] => 06067653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Data decorder and data decoding method' [patent_app_type] => 1 [patent_app_number] => 8/983067 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 8513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/067/06067653.pdf [firstpage_image] =>[orig_patent_app_number] => 983067 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/983067
Data decorder and data decoding method Dec 11, 1997 Issued
Array ( [id] => 3822667 [patent_doc_number] => 05832005 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Fault-tolerant method and means for managing access to an initial program load stored in read-only memory or the like' [patent_app_type] => 1 [patent_app_number] => 8/989058 [patent_app_country] => US [patent_app_date] => 1997-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4734 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/832/05832005.pdf [firstpage_image] =>[orig_patent_app_number] => 989058 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/989058
Fault-tolerant method and means for managing access to an initial program load stored in read-only memory or the like Dec 10, 1997 Issued
Array ( [id] => 4042982 [patent_doc_number] => 05931968 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Digital data recording channel' [patent_app_type] => 1 [patent_app_number] => 8/988679 [patent_app_country] => US [patent_app_date] => 1997-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 11542 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/931/05931968.pdf [firstpage_image] =>[orig_patent_app_number] => 988679 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/988679
Digital data recording channel Dec 10, 1997 Issued
Array ( [id] => 4335988 [patent_doc_number] => 06243844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Signal transmitter used in the transmission of data in a communication system' [patent_app_type] => 1 [patent_app_number] => 8/985634 [patent_app_country] => US [patent_app_date] => 1997-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4825 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243844.pdf [firstpage_image] =>[orig_patent_app_number] => 985634 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/985634
Signal transmitter used in the transmission of data in a communication system Dec 3, 1997 Issued
Array ( [id] => 3981619 [patent_doc_number] => 05887000 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Centralized test apparatus for ATM exchange system' [patent_app_type] => 1 [patent_app_number] => 8/966574 [patent_app_country] => US [patent_app_date] => 1997-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 5587 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/887/05887000.pdf [firstpage_image] =>[orig_patent_app_number] => 966574 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/966574
Centralized test apparatus for ATM exchange system Nov 9, 1997 Issued
Array ( [id] => 4122747 [patent_doc_number] => 06052808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Maintenance registers with Boundary Scan interface' [patent_app_type] => 1 [patent_app_number] => 8/962340 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 8230 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052808.pdf [firstpage_image] =>[orig_patent_app_number] => 962340 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962340
Maintenance registers with Boundary Scan interface Oct 30, 1997 Issued
Array ( [id] => 4118723 [patent_doc_number] => 06098185 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Header-formatted defective sector management system' [patent_app_type] => 1 [patent_app_number] => 8/961841 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3928 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/098/06098185.pdf [firstpage_image] =>[orig_patent_app_number] => 961841 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/961841
Header-formatted defective sector management system Oct 30, 1997 Issued
Array ( [id] => 4239803 [patent_doc_number] => 06088822 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Integrated circuit with tap controller' [patent_app_type] => 1 [patent_app_number] => 8/959890 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7812 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088822.pdf [firstpage_image] =>[orig_patent_app_number] => 959890 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/959890
Integrated circuit with tap controller Oct 28, 1997 Issued
Array ( [id] => 4236986 [patent_doc_number] => 06041427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Scan testable circuit arrangement' [patent_app_type] => 1 [patent_app_number] => 8/958530 [patent_app_country] => US [patent_app_date] => 1997-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4066 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041427.pdf [firstpage_image] =>[orig_patent_app_number] => 958530 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/958530
Scan testable circuit arrangement Oct 26, 1997 Issued
Array ( [id] => 4236971 [patent_doc_number] => 06041426 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Built in self test BIST for RAMS using a Johnson counter as a source of data' [patent_app_type] => 1 [patent_app_number] => 8/957262 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1777 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041426.pdf [firstpage_image] =>[orig_patent_app_number] => 957262 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/957262
Built in self test BIST for RAMS using a Johnson counter as a source of data Oct 23, 1997 Issued
Array ( [id] => 4209650 [patent_doc_number] => 06154863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Apparatus and method for testing non-componented printed circuit boards' [patent_app_type] => 1 [patent_app_number] => 8/956810 [patent_app_country] => US [patent_app_date] => 1997-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4936 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154863.pdf [firstpage_image] =>[orig_patent_app_number] => 956810 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/956810
Apparatus and method for testing non-componented printed circuit boards Oct 22, 1997 Issued
Array ( [id] => 4127357 [patent_doc_number] => 06058496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Self-timed AC CIO wrap method and apparatus' [patent_app_type] => 1 [patent_app_number] => 8/955442 [patent_app_country] => US [patent_app_date] => 1997-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 9629 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058496.pdf [firstpage_image] =>[orig_patent_app_number] => 955442 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/955442
Self-timed AC CIO wrap method and apparatus Oct 20, 1997 Issued
Array ( [id] => 4122761 [patent_doc_number] => 06052809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Method for generating test patterns' [patent_app_type] => 1 [patent_app_number] => 8/951782 [patent_app_country] => US [patent_app_date] => 1997-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4941 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052809.pdf [firstpage_image] =>[orig_patent_app_number] => 951782 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/951782
Method for generating test patterns Oct 15, 1997 Issued
Array ( [id] => 3971683 [patent_doc_number] => 06000051 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Method and apparatus for high-speed interconnect testing' [patent_app_type] => 1 [patent_app_number] => 8/948842 [patent_app_country] => US [patent_app_date] => 1997-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8299 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000051.pdf [firstpage_image] =>[orig_patent_app_number] => 948842 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/948842
Method and apparatus for high-speed interconnect testing Oct 9, 1997 Issued
Array ( [id] => 3940906 [patent_doc_number] => 05878061 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Providing serial data clock signal transitions with parity bits' [patent_app_type] => 1 [patent_app_number] => 8/948390 [patent_app_country] => US [patent_app_date] => 1997-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7360 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/878/05878061.pdf [firstpage_image] =>[orig_patent_app_number] => 948390 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/948390
Providing serial data clock signal transitions with parity bits Oct 9, 1997 Issued
Array ( [id] => 4025822 [patent_doc_number] => 06006353 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Error correction method for radio communication and radio communication apparatus' [patent_app_type] => 1 [patent_app_number] => 8/946979 [patent_app_country] => US [patent_app_date] => 1997-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3002 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/006/06006353.pdf [firstpage_image] =>[orig_patent_app_number] => 946979 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/946979
Error correction method for radio communication and radio communication apparatus Oct 7, 1997 Issued
Array ( [id] => 4025773 [patent_doc_number] => 06006350 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Semiconductor device testing apparatus and method for testing memory and logic sections of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/946991 [patent_app_country] => US [patent_app_date] => 1997-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3972 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/006/06006350.pdf [firstpage_image] =>[orig_patent_app_number] => 946991 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/946991
Semiconductor device testing apparatus and method for testing memory and logic sections of a semiconductor device Oct 7, 1997 Issued
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