Search

Christine Trinh Le Tu

Examiner (ID: 2588)

Most Active Art Unit
2117
Art Unit(s)
2313, 2133, 2111, 2117, 2784, 2785, 2138, 2413
Total Applications
1748
Issued Applications
1570
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16661554 [patent_doc_number] => 20210058191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => RECEIVER AND METHOD FOR PROCESSING A SIGNAL THEREOF [patent_app_type] => utility [patent_app_number] => 17/093105 [patent_app_country] => US [patent_app_date] => 2020-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11900 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17093105 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/093105
Receiver and method for processing a signal thereof Nov 8, 2020 Issued
Array ( [id] => 17506637 [patent_doc_number] => 20220099740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => CIRCUIT AND TESTING CIRCUIT THEREOF [patent_app_type] => utility [patent_app_number] => 17/084660 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17084660 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/084660
Circuit and testing circuit thereof Oct 29, 2020 Issued
Array ( [id] => 17506626 [patent_doc_number] => 20220099729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => AUTOMATED TESTING MACHINE WITH DATA PROCESSING FUNCTION AND INFORMATION PROCESSING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/083336 [patent_app_country] => US [patent_app_date] => 2020-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17083336 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/083336
Automated testing machine with data processing function and information processing method thereof Oct 28, 2020 Issued
Array ( [id] => 18047738 [patent_doc_number] => 11521696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Data input circuit and memory device including the same [patent_app_type] => utility [patent_app_number] => 17/077802 [patent_app_country] => US [patent_app_date] => 2020-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4582 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17077802 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/077802
Data input circuit and memory device including the same Oct 21, 2020 Issued
Array ( [id] => 16751389 [patent_doc_number] => 20210103398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => CODE WORD FORMAT AND STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/075235 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12637 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075235 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/075235
Code word format and structure Oct 19, 2020 Issued
Array ( [id] => 17477111 [patent_doc_number] => 20220084615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => TEST CIRCUIT USING CLOCK SIGNALS HAVING MUTUALLY DIFFERENT FREQUENCY [patent_app_type] => utility [patent_app_number] => 17/020529 [patent_app_country] => US [patent_app_date] => 2020-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17020529 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/020529
Test circuit using clock signals having mutually different frequency Sep 13, 2020 Issued
Array ( [id] => 16579347 [patent_doc_number] => 20210013748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => COMPOSITE INTEGRATED CIRCUITS AND METHODS FOR WIRELESS INTERACTIONS THEREWITH [patent_app_type] => utility [patent_app_number] => 17/015602 [patent_app_country] => US [patent_app_date] => 2020-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17015602 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/015602
Composite integrated circuits and methods for wireless interactions therewith Sep 8, 2020 Issued
Array ( [id] => 18103570 [patent_doc_number] => 11543452 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-03 [patent_title] => Hierarchical access simulation for signaling with more than two state values [patent_app_type] => utility [patent_app_number] => 17/014128 [patent_app_country] => US [patent_app_date] => 2020-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4064 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17014128 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/014128
Hierarchical access simulation for signaling with more than two state values Sep 7, 2020 Issued
Array ( [id] => 16529648 [patent_doc_number] => 20200403729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => PHY Error Indication Messaging [patent_app_type] => utility [patent_app_number] => 17/009638 [patent_app_country] => US [patent_app_date] => 2020-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17009638 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/009638
PHY error indication messaging Aug 31, 2020 Issued
Array ( [id] => 17422989 [patent_doc_number] => 11256443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Resource allocation in memory systems based on operation modes [patent_app_type] => utility [patent_app_number] => 17/008205 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7227 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17008205 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/008205
Resource allocation in memory systems based on operation modes Aug 30, 2020 Issued
Array ( [id] => 17437077 [patent_doc_number] => 11262402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Selectable JTAG or trace access with data store and output [patent_app_type] => utility [patent_app_number] => 17/003125 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 81 [patent_figures_cnt] => 114 [patent_no_of_words] => 40706 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003125 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/003125
Selectable JTAG or trace access with data store and output Aug 25, 2020 Issued
Array ( [id] => 19138704 [patent_doc_number] => 11973691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Data transmission method, device, and wireless network system [patent_app_type] => utility [patent_app_number] => 16/992784 [patent_app_country] => US [patent_app_date] => 2020-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 21166 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16992784 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/992784
Data transmission method, device, and wireless network system Aug 12, 2020 Issued
Array ( [id] => 16472513 [patent_doc_number] => 20200374051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => CONTROL MESSAGE RECEPTION AT A RECEIVER [patent_app_type] => utility [patent_app_number] => 16/992944 [patent_app_country] => US [patent_app_date] => 2020-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10016 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16992944 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/992944
Control message reception at a receiver Aug 12, 2020 Issued
Array ( [id] => 17402659 [patent_doc_number] => 20220044750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => MEMORY DEVICE TEST MODE ACCESS [patent_app_type] => utility [patent_app_number] => 16/986813 [patent_app_country] => US [patent_app_date] => 2020-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8497 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16986813 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/986813
Memory device test mode access Aug 5, 2020 Issued
Array ( [id] => 19107878 [patent_doc_number] => 11960989 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Read threshold estimation systems and methods using deep learning [patent_app_type] => utility [patent_app_number] => 16/937939 [patent_app_country] => US [patent_app_date] => 2020-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 10767 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16937939 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/937939
Read threshold estimation systems and methods using deep learning Jul 23, 2020 Issued
Array ( [id] => 17345793 [patent_doc_number] => 20220012124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => ASYMMETRIC LLR GENERATION USING ASSIST-READ [patent_app_type] => utility [patent_app_number] => 16/925160 [patent_app_country] => US [patent_app_date] => 2020-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7663 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16925160 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/925160
Asymmetric LLR generation using assist-read Jul 8, 2020 Issued
Array ( [id] => 18302882 [patent_doc_number] => 11624780 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => System and method for receiver equalization and stressed eye testing methodology for DDR5 memory controller [patent_app_type] => utility [patent_app_number] => 16/918762 [patent_app_country] => US [patent_app_date] => 2020-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 8998 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16918762 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/918762
System and method for receiver equalization and stressed eye testing methodology for DDR5 memory controller Jun 30, 2020 Issued
Array ( [id] => 16905783 [patent_doc_number] => 20210184699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => STORAGE CONTROLLER FOR CORRECTING ERROR, STORAGE DEVICE INCLUDING THE SAME, AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/917101 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12653 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16917101 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/917101
Storage controller for correcting error, storage device including the same, and operating method thereof Jun 29, 2020 Issued
Array ( [id] => 16928937 [patent_doc_number] => 11050437 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-29 [patent_title] => Implementation of invertible functions using party logic [patent_app_type] => utility [patent_app_number] => 16/913038 [patent_app_country] => US [patent_app_date] => 2020-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5948 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 411 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16913038 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/913038
Implementation of invertible functions using party logic Jun 25, 2020 Issued
Array ( [id] => 17319988 [patent_doc_number] => 20210409038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => OPTIMIZATIONS FOR VARIABLE SECTOR SIZE IN STORAGE DEVICE NAMESPACES [patent_app_type] => utility [patent_app_number] => 16/910893 [patent_app_country] => US [patent_app_date] => 2020-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6484 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16910893 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/910893
Optimizations for variable sector size in storage device namespaces Jun 23, 2020 Issued
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