Christine Trinh Le Tu

Array ( [id] => 3940160 [patent_doc_number] => 05954831 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Method for testing a memory device' [patent_app_type] => 1 [patent_app_number] => 8/947264 [patent_app_country] => US [patent_app_date] => 1997-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 30 [patent_no_of_words] => 3361 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/954/05954831.pdf [firstpage_image] =>[orig_patent_app_number] => 947264 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4022913 [patent_doc_number] => 05987631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Apparatus for measuring bit error ratio using a viterbi decoder' [patent_app_type] => 1 [patent_app_number] => 8/944647 [patent_app_country] => US [patent_app_date] => 1997-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3181 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987631.pdf [firstpage_image] =>[orig_patent_app_number] => 944647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3987471 [patent_doc_number] => 05905744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Test mode for multifunction PCI device' [patent_app_type] => 1 [patent_app_number] => 8/940866 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2612 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905744.pdf [firstpage_image] =>[orig_patent_app_number] => 940866 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3772523 [patent_doc_number] => 05852713 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'Computer data file backup system' [patent_app_type] => 1 [patent_app_number] => 8/940450 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3176 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/852/05852713.pdf [firstpage_image] =>[orig_patent_app_number] => 940450 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4252973 [patent_doc_number] => 06076177 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Method and apparatus for testing a circuit module concurrently with a non-volatile memory operation in a multi-module data processing system' [patent_app_type] => 1 [patent_app_number] => 8/935572 [patent_app_country] => US [patent_app_date] => 1997-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/076/06076177.pdf [firstpage_image] =>[orig_patent_app_number] => 935572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3874731 [patent_doc_number] => 05796759 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'System and method for assessing medical risk' [patent_app_type] => 1 [patent_app_number] => 8/927931 [patent_app_country] => US [patent_app_date] => 1997-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3721 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796759.pdf [firstpage_image] =>[orig_patent_app_number] => 927931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3916673 [patent_doc_number] => 05898713 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'IP checksum offload' [patent_app_type] => 1 [patent_app_number] => 8/921158 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3987 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898713.pdf [firstpage_image] =>[orig_patent_app_number] => 921158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3915941 [patent_doc_number] => 05944843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Method and apparatus for using the unused bits of a data packet to transmit additional information' [patent_app_type] => 1 [patent_app_number] => 8/918696 [patent_app_country] => US [patent_app_date] => 1997-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 9592 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/944/05944843.pdf [firstpage_image] =>[orig_patent_app_number] => 918696 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4101517 [patent_doc_number] => 06163861 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Error compensating method and apparatus and medium storing an error compensation program' [patent_app_type] => 1 [patent_app_number] => 8/915911 [patent_app_country] => US [patent_app_date] => 1997-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9493 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163861.pdf [firstpage_image] =>[orig_patent_app_number] => 915911 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4240543 [patent_doc_number] => 06012156 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Process and circuit arrangement for monitoring the function of a program-controlled circuit' [patent_app_type] => 1 [patent_app_number] => 8/860411 [patent_app_country] => US [patent_app_date] => 1997-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2450 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/012/06012156.pdf [firstpage_image] =>[orig_patent_app_number] => 860411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3924364 [patent_doc_number] => 05938785 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Automatically determining test patterns for a netlist having multiple clocks and sequential circuits' [patent_app_type] => 1 [patent_app_number] => 8/914431 [patent_app_country] => US [patent_app_date] => 1997-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4167 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/938/05938785.pdf [firstpage_image] =>[orig_patent_app_number] => 914431 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4239761 [patent_doc_number] => 06088819 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Dynamic semiconductor memory device and method of testing the same' [patent_app_type] => 1 [patent_app_number] => 8/910221 [patent_app_country] => US [patent_app_date] => 1997-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 11156 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088819.pdf [firstpage_image] =>[orig_patent_app_number] => 910221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3971251 [patent_doc_number] => 05991903 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Parallel bit test circuit for testing a semiconductor device in parallel bits' [patent_app_type] => 1 [patent_app_number] => 8/909300 [patent_app_country] => US [patent_app_date] => 1997-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 1519 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991903.pdf [firstpage_image] =>[orig_patent_app_number] => 909300 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4139479 [patent_doc_number] => 06073259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Low cost CMOS tester with high channel density' [patent_app_type] => 1 [patent_app_number] => 8/906532 [patent_app_country] => US [patent_app_date] => 1997-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9137 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073259.pdf [firstpage_image] =>[orig_patent_app_number] => 906532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3962628 [patent_doc_number] => 05974578 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Integrated circuit and test method therefor' [patent_app_type] => 1 [patent_app_number] => 8/906260 [patent_app_country] => US [patent_app_date] => 1997-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 5556 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974578.pdf [firstpage_image] =>[orig_patent_app_number] => 906260 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4167902 [patent_doc_number] => 06065143 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Semiconductor memory device capable of fast testing without externally considering address scramble or data scramble' [patent_app_type] => 1 [patent_app_number] => 8/905542 [patent_app_country] => US [patent_app_date] => 1997-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 35 [patent_no_of_words] => 10309 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/065/06065143.pdf [firstpage_image] =>[orig_patent_app_number] => 905542 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4037356 [patent_doc_number] => 05968195 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Estimation of failure section region with small simulation calculation quantity' [patent_app_type] => 1 [patent_app_number] => 8/905641 [patent_app_country] => US [patent_app_date] => 1997-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5860 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968195.pdf [firstpage_image] =>[orig_patent_app_number] => 905641 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4015441 [patent_doc_number] => 05925141 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Semiconductor memory device with data scramble circuit' [patent_app_type] => 1 [patent_app_number] => 8/904593 [patent_app_country] => US [patent_app_date] => 1997-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5515 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/925/05925141.pdf [firstpage_image] =>[orig_patent_app_number] => 904593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3974546 [patent_doc_number] => 05978958 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Data transmission system, data recording and reproducing apparatus and recording medium each having data structure of error correcting code' [patent_app_type] => 1 [patent_app_number] => 8/901527 [patent_app_country] => US [patent_app_date] => 1997-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 11958 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978958.pdf [firstpage_image] =>[orig_patent_app_number] => 901527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4058140 [patent_doc_number] => 05996095 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Set partitioning for sub-optimal decoding' [patent_app_type] => 1 [patent_app_number] => 8/910479 [patent_app_country] => US [patent_app_date] => 1997-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3112 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996095.pdf [firstpage_image] =>[orig_patent_app_number] => 910479 [rel_patent_id] =>[rel_patent_doc_number] =>)