Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3884049 [patent_doc_number] => 05838699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Line memory circuit' [patent_app_type] => 1 [patent_app_number] => 8/897001 [patent_app_country] => US [patent_app_date] => 1997-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 34 [patent_no_of_words] => 3278 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838699.pdf [firstpage_image] =>[orig_patent_app_number] => 897001 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/897001
Line memory circuit Jul 17, 1997 Issued
Array ( [id] => 3897139 [patent_doc_number] => 05894487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Error detection of directory arrays in dynamic circuits' [patent_app_type] => 1 [patent_app_number] => 8/892722 [patent_app_country] => US [patent_app_date] => 1997-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4891 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894487.pdf [firstpage_image] =>[orig_patent_app_number] => 892722 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/892722
Error detection of directory arrays in dynamic circuits Jul 14, 1997 Issued
Array ( [id] => 4005987 [patent_doc_number] => 05892780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Data storage system and parity generation method for data storage system' [patent_app_type] => 1 [patent_app_number] => 8/893011 [patent_app_country] => US [patent_app_date] => 1997-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 7187 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892780.pdf [firstpage_image] =>[orig_patent_app_number] => 893011 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/893011
Data storage system and parity generation method for data storage system Jul 14, 1997 Issued
Array ( [id] => 3897060 [patent_doc_number] => 05894482 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Semiconductor integrated circuit with a testable block' [patent_app_type] => 1 [patent_app_number] => 8/890976 [patent_app_country] => US [patent_app_date] => 1997-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6543 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894482.pdf [firstpage_image] =>[orig_patent_app_number] => 890976 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/890976
Semiconductor integrated circuit with a testable block Jul 9, 1997 Issued
Array ( [id] => 3889894 [patent_doc_number] => 05764660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Processor independent error checking arrangement' [patent_app_type] => 1 [patent_app_number] => 8/890278 [patent_app_country] => US [patent_app_date] => 1997-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1812 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764660.pdf [firstpage_image] =>[orig_patent_app_number] => 890278 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/890278
Processor independent error checking arrangement Jul 8, 1997 Issued
Array ( [id] => 4426768 [patent_doc_number] => 06178533 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Method and system for design verification' [patent_app_type] => 1 [patent_app_number] => 8/885160 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3273 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178533.pdf [firstpage_image] =>[orig_patent_app_number] => 885160 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/885160
Method and system for design verification Jun 29, 1997 Issued
Array ( [id] => 3915972 [patent_doc_number] => 05944845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Circuit and method to prevent inadvertent test mode entry' [patent_app_type] => 1 [patent_app_number] => 8/883181 [patent_app_country] => US [patent_app_date] => 1997-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2373 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/944/05944845.pdf [firstpage_image] =>[orig_patent_app_number] => 883181 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/883181
Circuit and method to prevent inadvertent test mode entry Jun 25, 1997 Issued
Array ( [id] => 3971650 [patent_doc_number] => 06000049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Physical packaging position information processing system' [patent_app_type] => 1 [patent_app_number] => 8/883451 [patent_app_country] => US [patent_app_date] => 1997-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3201 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000049.pdf [firstpage_image] =>[orig_patent_app_number] => 883451 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/883451
Physical packaging position information processing system Jun 25, 1997 Issued
Array ( [id] => 4216103 [patent_doc_number] => 06014762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Method and apparatus for scan test of SRAM for microprocessor without full scan capability' [patent_app_type] => 1 [patent_app_number] => 8/880230 [patent_app_country] => US [patent_app_date] => 1997-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3254 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014762.pdf [firstpage_image] =>[orig_patent_app_number] => 880230 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/880230
Method and apparatus for scan test of SRAM for microprocessor without full scan capability Jun 22, 1997 Issued
Array ( [id] => 4162978 [patent_doc_number] => 06032274 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Method and apparatus for compressed data testing of more than one memory array' [patent_app_type] => 1 [patent_app_number] => 8/879409 [patent_app_country] => US [patent_app_date] => 1997-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5526 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/032/06032274.pdf [firstpage_image] =>[orig_patent_app_number] => 879409 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/879409
Method and apparatus for compressed data testing of more than one memory array Jun 19, 1997 Issued
Array ( [id] => 3916468 [patent_doc_number] => 05898699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Digital broadcast receiver and signal level display method' [patent_app_type] => 1 [patent_app_number] => 8/874368 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2375 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898699.pdf [firstpage_image] =>[orig_patent_app_number] => 874368 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/874368
Digital broadcast receiver and signal level display method Jun 18, 1997 Issued
Array ( [id] => 4074313 [patent_doc_number] => 05896392 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Device and method for automatically controlling decision points' [patent_app_type] => 1 [patent_app_number] => 8/878946 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5628 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896392.pdf [firstpage_image] =>[orig_patent_app_number] => 878946 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/878946
Device and method for automatically controlling decision points Jun 18, 1997 Issued
Array ( [id] => 3916539 [patent_doc_number] => 05898704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Processing system having testing mechanism' [patent_app_type] => 1 [patent_app_number] => 8/878121 [patent_app_country] => US [patent_app_date] => 1997-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9118 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898704.pdf [firstpage_image] =>[orig_patent_app_number] => 878121 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/878121
Processing system having testing mechanism Jun 17, 1997 Issued
Array ( [id] => 3971332 [patent_doc_number] => 05936972 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Syndrome-based channel quality or message structure determiner' [patent_app_type] => 1 [patent_app_number] => 8/878280 [patent_app_country] => US [patent_app_date] => 1997-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5349 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936972.pdf [firstpage_image] =>[orig_patent_app_number] => 878280 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/878280
Syndrome-based channel quality or message structure determiner Jun 17, 1997 Issued
Array ( [id] => 3945564 [patent_doc_number] => 05935264 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Method and apparatus for determining a set of tests for integrated circuit testing' [patent_app_type] => 1 [patent_app_number] => 8/872240 [patent_app_country] => US [patent_app_date] => 1997-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3102 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/935/05935264.pdf [firstpage_image] =>[orig_patent_app_number] => 872240 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/872240
Method and apparatus for determining a set of tests for integrated circuit testing Jun 9, 1997 Issued
Array ( [id] => 1539429 [patent_doc_number] => 06412094 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Method and circuit for performing 3/5 major voting' [patent_app_type] => B1 [patent_app_number] => 08/871442 [patent_app_country] => US [patent_app_date] => 1997-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2379 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/412/06412094.pdf [firstpage_image] =>[orig_patent_app_number] => 08871442 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/871442
Method and circuit for performing 3/5 major voting Jun 8, 1997 Issued
Array ( [id] => 3806434 [patent_doc_number] => 05841968 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Processor circuit with testing device' [patent_app_type] => 1 [patent_app_number] => 8/871677 [patent_app_country] => US [patent_app_date] => 1997-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1860 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841968.pdf [firstpage_image] =>[orig_patent_app_number] => 871677 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/871677
Processor circuit with testing device Jun 5, 1997 Issued
Array ( [id] => 3916510 [patent_doc_number] => 05898702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Mutual exclusivity circuit for use in test pattern application scan architecture circuits' [patent_app_type] => 1 [patent_app_number] => 8/867892 [patent_app_country] => US [patent_app_date] => 1997-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 5260 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898702.pdf [firstpage_image] =>[orig_patent_app_number] => 867892 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/867892
Mutual exclusivity circuit for use in test pattern application scan architecture circuits Jun 2, 1997 Issued
08/868340 SCAN BASED PATH DELAY TESTING OF INTEGRATED CIRCUITS CONTAINING EMBEDDED MEMORY ELEMENTS Jun 2, 1997 Abandoned
Array ( [id] => 3883964 [patent_doc_number] => 05838693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Partial scan logic' [patent_app_type] => 1 [patent_app_number] => 8/856942 [patent_app_country] => US [patent_app_date] => 1997-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5082 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838693.pdf [firstpage_image] =>[orig_patent_app_number] => 856942 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/856942
Partial scan logic May 14, 1997 Issued
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