Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3916522 [patent_doc_number] => 05951702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'RAM-like test structure superimposed over rows of macrocells with added differential pass transistors in a CPU' [patent_app_type] => 1 [patent_app_number] => 8/832922 [patent_app_country] => US [patent_app_date] => 1997-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7757 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/951/05951702.pdf [firstpage_image] =>[orig_patent_app_number] => 832922 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/832922
RAM-like test structure superimposed over rows of macrocells with added differential pass transistors in a CPU Apr 3, 1997 Issued
Array ( [id] => 3775920 [patent_doc_number] => 05844912 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Fast verify for CMOS memory cells' [patent_app_type] => 1 [patent_app_number] => 8/831372 [patent_app_country] => US [patent_app_date] => 1997-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4197 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 478 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844912.pdf [firstpage_image] =>[orig_patent_app_number] => 831372 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/831372
Fast verify for CMOS memory cells Mar 31, 1997 Issued
Array ( [id] => 3940972 [patent_doc_number] => 05878064 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Method for detecting and reporting failures in EPL systems' [patent_app_type] => 1 [patent_app_number] => 8/826264 [patent_app_country] => US [patent_app_date] => 1997-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2444 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/878/05878064.pdf [firstpage_image] =>[orig_patent_app_number] => 826264 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/826264
Method for detecting and reporting failures in EPL systems Mar 26, 1997 Issued
Array ( [id] => 4068298 [patent_doc_number] => 05864570 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Method and apparatus for communicating selected additional data in a data stream of fixed size' [patent_app_type] => 1 [patent_app_number] => 8/824388 [patent_app_country] => US [patent_app_date] => 1997-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4170 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/864/05864570.pdf [firstpage_image] =>[orig_patent_app_number] => 824388 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/824388
Method and apparatus for communicating selected additional data in a data stream of fixed size Mar 25, 1997 Issued
Array ( [id] => 3914518 [patent_doc_number] => 05751745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Memory implemented error detection and correction code with address parity bits' [patent_app_type] => 1 [patent_app_number] => 8/824098 [patent_app_country] => US [patent_app_date] => 1997-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 11618 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751745.pdf [firstpage_image] =>[orig_patent_app_number] => 824098 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/824098
Memory implemented error detection and correction code with address parity bits Mar 24, 1997 Issued
Array ( [id] => 3846750 [patent_doc_number] => 05815513 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Test pattern preparation system' [patent_app_type] => 1 [patent_app_number] => 8/821728 [patent_app_country] => US [patent_app_date] => 1997-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 4018 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815513.pdf [firstpage_image] =>[orig_patent_app_number] => 821728 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/821728
Test pattern preparation system Mar 19, 1997 Issued
Array ( [id] => 3799169 [patent_doc_number] => 05822332 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Pseudonoise code pull in circuit' [patent_app_type] => 1 [patent_app_number] => 8/816836 [patent_app_country] => US [patent_app_date] => 1997-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 3336 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822332.pdf [firstpage_image] =>[orig_patent_app_number] => 816836 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/816836
Pseudonoise code pull in circuit Mar 12, 1997 Issued
Array ( [id] => 3971237 [patent_doc_number] => 05991902 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Memory apparatus and data processor using the same' [patent_app_type] => 1 [patent_app_number] => 8/812464 [patent_app_country] => US [patent_app_date] => 1997-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 25335 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991902.pdf [firstpage_image] =>[orig_patent_app_number] => 812464 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/812464
Memory apparatus and data processor using the same Mar 5, 1997 Issued
Array ( [id] => 3816477 [patent_doc_number] => 05854795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Memory capacity test method and computer system' [patent_app_type] => 1 [patent_app_number] => 8/801919 [patent_app_country] => US [patent_app_date] => 1997-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2792 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854795.pdf [firstpage_image] =>[orig_patent_app_number] => 801919 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/801919
Memory capacity test method and computer system Feb 13, 1997 Issued
Array ( [id] => 3994980 [patent_doc_number] => 05862157 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Method and circuitry for monitoring a digital channel' [patent_app_type] => 1 [patent_app_number] => 8/804867 [patent_app_country] => US [patent_app_date] => 1997-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 8396 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/862/05862157.pdf [firstpage_image] =>[orig_patent_app_number] => 804867 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/804867
Method and circuitry for monitoring a digital channel Feb 1, 1997 Issued
Array ( [id] => 4040269 [patent_doc_number] => 05908471 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Diagnostic arrangement for digital computer system' [patent_app_type] => 1 [patent_app_number] => 8/792506 [patent_app_country] => US [patent_app_date] => 1997-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 10012 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/908/05908471.pdf [firstpage_image] =>[orig_patent_app_number] => 792506 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/792506
Diagnostic arrangement for digital computer system Jan 30, 1997 Issued
Array ( [id] => 4028176 [patent_doc_number] => 05881067 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Flip-flop design and technique for scan chain diagnosis' [patent_app_type] => 1 [patent_app_number] => 8/789256 [patent_app_country] => US [patent_app_date] => 1997-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3908 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/881/05881067.pdf [firstpage_image] =>[orig_patent_app_number] => 789256 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/789256
Flip-flop design and technique for scan chain diagnosis Jan 27, 1997 Issued
Array ( [id] => 4065193 [patent_doc_number] => 05933434 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Memory system having internal state monitoring circuit' [patent_app_type] => 1 [patent_app_number] => 8/789836 [patent_app_country] => US [patent_app_date] => 1997-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5017 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933434.pdf [firstpage_image] =>[orig_patent_app_number] => 789836 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/789836
Memory system having internal state monitoring circuit Jan 27, 1997 Issued
Array ( [id] => 4074352 [patent_doc_number] => 05896394 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Data structure, data communication method, apparatus and communication terminal apparatus' [patent_app_type] => 1 [patent_app_number] => 8/789476 [patent_app_country] => US [patent_app_date] => 1997-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7842 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896394.pdf [firstpage_image] =>[orig_patent_app_number] => 789476 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/789476
Data structure, data communication method, apparatus and communication terminal apparatus Jan 26, 1997 Issued
Array ( [id] => 3989706 [patent_doc_number] => 05917831 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'System for testing a data-transmission network' [patent_app_type] => 1 [patent_app_number] => 8/776718 [patent_app_country] => US [patent_app_date] => 1997-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3215 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917831.pdf [firstpage_image] =>[orig_patent_app_number] => 776718 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/776718
System for testing a data-transmission network Jan 20, 1997 Issued
Array ( [id] => 4078737 [patent_doc_number] => 05867503 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Digital sound broadcasting receiver and automatic phase controlling method therefor' [patent_app_type] => 1 [patent_app_number] => 8/785506 [patent_app_country] => US [patent_app_date] => 1997-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 8039 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867503.pdf [firstpage_image] =>[orig_patent_app_number] => 785506 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/785506
Digital sound broadcasting receiver and automatic phase controlling method therefor Jan 16, 1997 Issued
Array ( [id] => 4055631 [patent_doc_number] => 05875201 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Second level cache having instruction cache parity error control' [patent_app_type] => 1 [patent_app_number] => 8/777037 [patent_app_country] => US [patent_app_date] => 1996-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 18283 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875201.pdf [firstpage_image] =>[orig_patent_app_number] => 777037 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/777037
Second level cache having instruction cache parity error control Dec 29, 1996 Issued
Array ( [id] => 3940132 [patent_doc_number] => 05954829 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'System, method, and computer program product for digital cross connect testing' [patent_app_type] => 1 [patent_app_number] => 8/774650 [patent_app_country] => US [patent_app_date] => 1996-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 20719 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/954/05954829.pdf [firstpage_image] =>[orig_patent_app_number] => 774650 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/774650
System, method, and computer program product for digital cross connect testing Dec 29, 1996 Issued
Array ( [id] => 3997608 [patent_doc_number] => 05961657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Parallel test circuit for semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/770671 [patent_app_country] => US [patent_app_date] => 1996-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 2907 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/961/05961657.pdf [firstpage_image] =>[orig_patent_app_number] => 770671 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/770671
Parallel test circuit for semiconductor memory device Dec 19, 1996 Issued
Array ( [id] => 4161186 [patent_doc_number] => 06061809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Process control interface system having triply redundant remote field units' [patent_app_type] => 1 [patent_app_number] => 8/769915 [patent_app_country] => US [patent_app_date] => 1996-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 209 [patent_figures_cnt] => 271 [patent_no_of_words] => 55341 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061809.pdf [firstpage_image] =>[orig_patent_app_number] => 769915 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/769915
Process control interface system having triply redundant remote field units Dec 18, 1996 Issued
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