Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3968113 [patent_doc_number] => 05983375 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Multi-bit test circuit and method thereof' [patent_app_type] => 1 [patent_app_number] => 8/766116 [patent_app_country] => US [patent_app_date] => 1996-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4852 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983375.pdf [firstpage_image] =>[orig_patent_app_number] => 766116 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/766116
Multi-bit test circuit and method thereof Dec 15, 1996 Issued
Array ( [id] => 4055353 [patent_doc_number] => 05912900 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Method and system for testing self-timed circuitry' [patent_app_type] => 1 [patent_app_number] => 8/767244 [patent_app_country] => US [patent_app_date] => 1996-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9998 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912900.pdf [firstpage_image] =>[orig_patent_app_number] => 767244 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/767244
Method and system for testing self-timed circuitry Dec 12, 1996 Issued
Array ( [id] => 3822581 [patent_doc_number] => 05831998 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Method of testcase optimization' [patent_app_type] => 1 [patent_app_number] => 8/766791 [patent_app_country] => US [patent_app_date] => 1996-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5302 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/831/05831998.pdf [firstpage_image] =>[orig_patent_app_number] => 766791 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/766791
Method of testcase optimization Dec 12, 1996 Issued
Array ( [id] => 3934338 [patent_doc_number] => 05954435 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Memory apparatus and data processor using the same' [patent_app_type] => 1 [patent_app_number] => 8/768021 [patent_app_country] => US [patent_app_date] => 1996-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 25347 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/954/05954435.pdf [firstpage_image] =>[orig_patent_app_number] => 768021 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/768021
Memory apparatus and data processor using the same Dec 12, 1996 Issued
Array ( [id] => 3989721 [patent_doc_number] => 05917832 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Self-test circuit and method utilizing interlaced scanning for testing a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/757970 [patent_app_country] => US [patent_app_date] => 1996-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3279 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917832.pdf [firstpage_image] =>[orig_patent_app_number] => 757970 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/757970
Self-test circuit and method utilizing interlaced scanning for testing a semiconductor memory device Dec 4, 1996 Issued
Array ( [id] => 3810283 [patent_doc_number] => 05828673 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Logical check apparatus and method for semiconductor circuits and storage medium storing logical check program for semiconductor circuits' [patent_app_type] => 1 [patent_app_number] => 8/760291 [patent_app_country] => US [patent_app_date] => 1996-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5450 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828673.pdf [firstpage_image] =>[orig_patent_app_number] => 760291 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/760291
Logical check apparatus and method for semiconductor circuits and storage medium storing logical check program for semiconductor circuits Dec 3, 1996 Issued
Array ( [id] => 4058405 [patent_doc_number] => 05996113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method and apparatus for generating digital checksum signatures for alteration detection and version confirmation' [patent_app_type] => 1 [patent_app_number] => 8/753389 [patent_app_country] => US [patent_app_date] => 1996-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4656 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996113.pdf [firstpage_image] =>[orig_patent_app_number] => 753389 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/753389
Method and apparatus for generating digital checksum signatures for alteration detection and version confirmation Nov 25, 1996 Issued
08/752286 SIMULATION DEVICE AND METHOD Nov 18, 1996 Abandoned
Array ( [id] => 3841915 [patent_doc_number] => 05712856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Method and apparatus for testing links between network switches' [patent_app_type] => 1 [patent_app_number] => 8/749880 [patent_app_country] => US [patent_app_date] => 1996-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2702 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/712/05712856.pdf [firstpage_image] =>[orig_patent_app_number] => 749880 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/749880
Method and apparatus for testing links between network switches Nov 14, 1996 Issued
Array ( [id] => 3933571 [patent_doc_number] => 05914966 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'System for the monitoring and management of a point-to-multipoint access network' [patent_app_type] => 1 [patent_app_number] => 8/747626 [patent_app_country] => US [patent_app_date] => 1996-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4460 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/914/05914966.pdf [firstpage_image] =>[orig_patent_app_number] => 747626 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/747626
System for the monitoring and management of a point-to-multipoint access network Nov 12, 1996 Issued
Array ( [id] => 3757670 [patent_doc_number] => 05754759 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Testing and monitoring of programmed devices' [patent_app_type] => 1 [patent_app_number] => 8/748454 [patent_app_country] => US [patent_app_date] => 1996-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 8142 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754759.pdf [firstpage_image] =>[orig_patent_app_number] => 748454 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/748454
Testing and monitoring of programmed devices Nov 12, 1996 Issued
Array ( [id] => 3989850 [patent_doc_number] => 05917841 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Code error detecting circuit' [patent_app_type] => 1 [patent_app_number] => 8/748509 [patent_app_country] => US [patent_app_date] => 1996-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9149 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917841.pdf [firstpage_image] =>[orig_patent_app_number] => 748509 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/748509
Code error detecting circuit Nov 7, 1996 Issued
Array ( [id] => 3914345 [patent_doc_number] => 05751734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Decoding method and apparatus using trace deletion for Viterbi algorithm' [patent_app_type] => 1 [patent_app_number] => 8/742663 [patent_app_country] => US [patent_app_date] => 1996-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2867 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751734.pdf [firstpage_image] =>[orig_patent_app_number] => 742663 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/742663
Decoding method and apparatus using trace deletion for Viterbi algorithm Nov 3, 1996 Issued
Array ( [id] => 3971340 [patent_doc_number] => 05991909 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Parallel decompressor and related methods and apparatuses' [patent_app_type] => 1 [patent_app_number] => 8/730066 [patent_app_country] => US [patent_app_date] => 1996-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6611 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991909.pdf [firstpage_image] =>[orig_patent_app_number] => 730066 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/730066
Parallel decompressor and related methods and apparatuses Oct 14, 1996 Issued
Array ( [id] => 3846656 [patent_doc_number] => 05815508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Method and apparatus for providing information between communication devices' [patent_app_type] => 1 [patent_app_number] => 8/728719 [patent_app_country] => US [patent_app_date] => 1996-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3826 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815508.pdf [firstpage_image] =>[orig_patent_app_number] => 728719 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/728719
Method and apparatus for providing information between communication devices Oct 10, 1996 Issued
Array ( [id] => 7638564 [patent_doc_number] => 06397357 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Method of testing detection and correction capabilities of ECC memory controller' [patent_app_type] => B1 [patent_app_number] => 08/727256 [patent_app_country] => US [patent_app_date] => 1996-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2069 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397357.pdf [firstpage_image] =>[orig_patent_app_number] => 08727256 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/727256
Method of testing detection and correction capabilities of ECC memory controller Oct 7, 1996 Issued
Array ( [id] => 3918285 [patent_doc_number] => 05898825 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Failed command translation technique' [patent_app_type] => 1 [patent_app_number] => 8/710906 [patent_app_country] => US [patent_app_date] => 1996-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1839 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898825.pdf [firstpage_image] =>[orig_patent_app_number] => 710906 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/710906
Failed command translation technique Sep 23, 1996 Issued
Array ( [id] => 3948546 [patent_doc_number] => 05940415 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Error tolerant addressing system and method for noisy ATM links' [patent_app_type] => 1 [patent_app_number] => 8/710296 [patent_app_country] => US [patent_app_date] => 1996-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3392 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940415.pdf [firstpage_image] =>[orig_patent_app_number] => 710296 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/710296
Error tolerant addressing system and method for noisy ATM links Sep 16, 1996 Issued
Array ( [id] => 3848977 [patent_doc_number] => 05815651 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Method and apparatus for CPU failure recovery in symmetric multi-processing systems' [patent_app_type] => 1 [patent_app_number] => 8/711386 [patent_app_country] => US [patent_app_date] => 1996-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6190 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 377 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815651.pdf [firstpage_image] =>[orig_patent_app_number] => 711386 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/711386
Method and apparatus for CPU failure recovery in symmetric multi-processing systems Sep 5, 1996 Issued
Array ( [id] => 3940257 [patent_doc_number] => 05954838 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Data storage system having row/column address parity checking' [patent_app_type] => 1 [patent_app_number] => 8/701868 [patent_app_country] => US [patent_app_date] => 1996-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 29 [patent_no_of_words] => 8132 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/954/05954838.pdf [firstpage_image] =>[orig_patent_app_number] => 701868 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/701868
Data storage system having row/column address parity checking Aug 22, 1996 Issued
Menu