Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3897129 [patent_doc_number] => 05894486 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Coding/decoding apparatus' [patent_app_type] => 1 [patent_app_number] => 8/630880 [patent_app_country] => US [patent_app_date] => 1996-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2021 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894486.pdf [firstpage_image] =>[orig_patent_app_number] => 630880 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/630880
Coding/decoding apparatus Apr 1, 1996 Issued
Array ( [id] => 3639660 [patent_doc_number] => 05687178 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-11 [patent_title] => 'Method and apparatus for testing a static RAM' [patent_app_type] => 1 [patent_app_number] => 8/621370 [patent_app_country] => US [patent_app_date] => 1996-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5477 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/687/05687178.pdf [firstpage_image] =>[orig_patent_app_number] => 621370 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/621370
Method and apparatus for testing a static RAM Mar 24, 1996 Issued
Array ( [id] => 3748300 [patent_doc_number] => 05699364 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Data communication system, apparatus and method which optimize the set value of parameters' [patent_app_type] => 1 [patent_app_number] => 8/616565 [patent_app_country] => US [patent_app_date] => 1996-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5605 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/699/05699364.pdf [firstpage_image] =>[orig_patent_app_number] => 616565 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/616565
Data communication system, apparatus and method which optimize the set value of parameters Mar 14, 1996 Issued
08/615737 PROVIDING SERIAL DATA CLOCK SIGNAL TRANSITIONS WITH PARITY BITS Mar 13, 1996 Abandoned
Array ( [id] => 3639630 [patent_doc_number] => 05621883 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-15 [patent_title] => 'Circuit for testing microprocessor memories' [patent_app_type] => 1 [patent_app_number] => 8/613597 [patent_app_country] => US [patent_app_date] => 1996-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6058 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/621/05621883.pdf [firstpage_image] =>[orig_patent_app_number] => 613597 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/613597
Circuit for testing microprocessor memories Mar 10, 1996 Issued
Array ( [id] => 4028167 [patent_doc_number] => 05881066 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'System for testing a transmission link' [patent_app_type] => 1 [patent_app_number] => 8/607958 [patent_app_country] => US [patent_app_date] => 1996-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1957 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/881/05881066.pdf [firstpage_image] =>[orig_patent_app_number] => 607958 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/607958
System for testing a transmission link Feb 28, 1996 Issued
Array ( [id] => 3842007 [patent_doc_number] => 05712863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Randomizing encoder for digital data storage' [patent_app_type] => 1 [patent_app_number] => 8/599146 [patent_app_country] => US [patent_app_date] => 1996-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 10228 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/712/05712863.pdf [firstpage_image] =>[orig_patent_app_number] => 599146 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/599146
Randomizing encoder for digital data storage Feb 8, 1996 Issued
Array ( [id] => 3670570 [patent_doc_number] => 05648973 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'I/O toggle test method using JTAG' [patent_app_type] => 1 [patent_app_number] => 8/596043 [patent_app_country] => US [patent_app_date] => 1996-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5014 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/648/05648973.pdf [firstpage_image] =>[orig_patent_app_number] => 596043 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/596043
I/O toggle test method using JTAG Feb 5, 1996 Issued
Array ( [id] => 3875388 [patent_doc_number] => 05793780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Method for monitoring transmission of digital data signals on two parallel data lines' [patent_app_type] => 1 [patent_app_number] => 8/592996 [patent_app_country] => US [patent_app_date] => 1996-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1522 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793780.pdf [firstpage_image] =>[orig_patent_app_number] => 592996 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/592996
Method for monitoring transmission of digital data signals on two parallel data lines Jan 28, 1996 Issued
Array ( [id] => 3773534 [patent_doc_number] => 05742625 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-21 [patent_title] => 'Data storage system and parity generation method for data storage system' [patent_app_type] => 1 [patent_app_number] => 8/592281 [patent_app_country] => US [patent_app_date] => 1996-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 7107 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/742/05742625.pdf [firstpage_image] =>[orig_patent_app_number] => 592281 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/592281
Data storage system and parity generation method for data storage system Jan 25, 1996 Issued
Array ( [id] => 3890711 [patent_doc_number] => 05825782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Non-volatile memory system including apparatus for testing memory elements by writing and verifying data patterns' [patent_app_type] => 1 [patent_app_number] => 8/589754 [patent_app_country] => US [patent_app_date] => 1996-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9767 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825782.pdf [firstpage_image] =>[orig_patent_app_number] => 589754 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/589754
Non-volatile memory system including apparatus for testing memory elements by writing and verifying data patterns Jan 21, 1996 Issued
Array ( [id] => 4039878 [patent_doc_number] => 05903582 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Memory circuit' [patent_app_type] => 1 [patent_app_number] => 8/588237 [patent_app_country] => US [patent_app_date] => 1996-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4591 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903582.pdf [firstpage_image] =>[orig_patent_app_number] => 588237 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/588237
Memory circuit Jan 17, 1996 Issued
Array ( [id] => 3826242 [patent_doc_number] => 05812558 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Device and method for generating multiplexed signals with real time inputs for testing voice grade channels in a demultiplexer' [patent_app_type] => 1 [patent_app_number] => 8/586320 [patent_app_country] => US [patent_app_date] => 1996-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3452 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812558.pdf [firstpage_image] =>[orig_patent_app_number] => 586320 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/586320
Device and method for generating multiplexed signals with real time inputs for testing voice grade channels in a demultiplexer Jan 16, 1996 Issued
Array ( [id] => 3736899 [patent_doc_number] => 05652754 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Signature analysis usage for fault isolation' [patent_app_type] => 1 [patent_app_number] => 8/579523 [patent_app_country] => US [patent_app_date] => 1995-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1831 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652754.pdf [firstpage_image] =>[orig_patent_app_number] => 579523 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/579523
Signature analysis usage for fault isolation Dec 26, 1995 Issued
Array ( [id] => 3704510 [patent_doc_number] => 05661735 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'FDIC method for minimizing measuring failures in a measuring system comprising redundant sensors' [patent_app_type] => 1 [patent_app_number] => 8/578840 [patent_app_country] => US [patent_app_date] => 1995-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5443 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661735.pdf [firstpage_image] =>[orig_patent_app_number] => 578840 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/578840
FDIC method for minimizing measuring failures in a measuring system comprising redundant sensors Dec 25, 1995 Issued
Array ( [id] => 3859555 [patent_doc_number] => 05719889 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-17 [patent_title] => 'Programmable parity checking and comparison circuit' [patent_app_type] => 1 [patent_app_number] => 8/575314 [patent_app_country] => US [patent_app_date] => 1995-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4880 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/719/05719889.pdf [firstpage_image] =>[orig_patent_app_number] => 575314 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/575314
Programmable parity checking and comparison circuit Dec 19, 1995 Issued
Array ( [id] => 3644671 [patent_doc_number] => 05631912 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-20 [patent_title] => 'High impedance test mode for JTAG' [patent_app_type] => 1 [patent_app_number] => 8/574593 [patent_app_country] => US [patent_app_date] => 1995-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3710 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/631/05631912.pdf [firstpage_image] =>[orig_patent_app_number] => 574593 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/574593
High impedance test mode for JTAG Dec 18, 1995 Issued
08/574088 PROCESSOR INDEPENDENT ERROR CHECKING ARRANGEMENT Dec 17, 1995 Abandoned
Array ( [id] => 3805285 [patent_doc_number] => 05726992 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Circuit for and method of assessing an RDS signal' [patent_app_type] => 1 [patent_app_number] => 8/569781 [patent_app_country] => US [patent_app_date] => 1995-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3855 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/726/05726992.pdf [firstpage_image] =>[orig_patent_app_number] => 569781 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/569781
Circuit for and method of assessing an RDS signal Dec 7, 1995 Issued
08/568733 PARTIAL SCAN LOGIC Dec 4, 1995 Abandoned
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