Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3825760 [patent_doc_number] => 05832210 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Device and method for controlling communication' [patent_app_type] => 1 [patent_app_number] => 8/504079 [patent_app_country] => US [patent_app_date] => 1995-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9658 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/832/05832210.pdf [firstpage_image] =>[orig_patent_app_number] => 504079 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/504079
Device and method for controlling communication Jul 18, 1995 Issued
Array ( [id] => 3698613 [patent_doc_number] => 05663963 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Method for detecting and reporting failures in EPL systems' [patent_app_type] => 1 [patent_app_number] => 8/503144 [patent_app_country] => US [patent_app_date] => 1995-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2443 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/663/05663963.pdf [firstpage_image] =>[orig_patent_app_number] => 503144 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/503144
Method for detecting and reporting failures in EPL systems Jul 16, 1995 Issued
Array ( [id] => 3733746 [patent_doc_number] => 05673269 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-30 [patent_title] => 'Method and apparatus for detecting valid data peaks' [patent_app_type] => 1 [patent_app_number] => 8/502195 [patent_app_country] => US [patent_app_date] => 1995-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6402 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/673/05673269.pdf [firstpage_image] =>[orig_patent_app_number] => 502195 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/502195
Method and apparatus for detecting valid data peaks Jul 12, 1995 Issued
Array ( [id] => 3670554 [patent_doc_number] => 05648972 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'V.35 integrated circuit transceiver with diagnostics loopback' [patent_app_type] => 1 [patent_app_number] => 8/500758 [patent_app_country] => US [patent_app_date] => 1995-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2002 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/648/05648972.pdf [firstpage_image] =>[orig_patent_app_number] => 500758 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/500758
V.35 integrated circuit transceiver with diagnostics loopback Jul 10, 1995 Issued
Array ( [id] => 3531167 [patent_doc_number] => 05490156 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'Cross-coupled parity circuit with charging circuitry to improve response time' [patent_app_type] => 1 [patent_app_number] => 8/493018 [patent_app_country] => US [patent_app_date] => 1995-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2403 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/490/05490156.pdf [firstpage_image] =>[orig_patent_app_number] => 493018 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/493018
Cross-coupled parity circuit with charging circuitry to improve response time Jun 20, 1995 Issued
Array ( [id] => 1567692 [patent_doc_number] => 06438720 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Host port interface' [patent_app_type] => B1 [patent_app_number] => 08/488394 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 29621 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438720.pdf [firstpage_image] =>[orig_patent_app_number] => 08488394 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/488394
Host port interface Jun 6, 1995 Issued
Array ( [id] => 3705410 [patent_doc_number] => 05596585 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Performance driven BIST technique' [patent_app_type] => 1 [patent_app_number] => 8/482223 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6078 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/596/05596585.pdf [firstpage_image] =>[orig_patent_app_number] => 482223 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/482223
Performance driven BIST technique Jun 6, 1995 Issued
08/484995 PROCESS CONTROL INTERFACE SYSTEM HAVING TRIPLY REDUNDANT REMOTE FIELD UNITS Jun 6, 1995 Abandoned
Array ( [id] => 4209623 [patent_doc_number] => 06154861 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method and apparatus for built-in self-test of smart memories' [patent_app_type] => 1 [patent_app_number] => 8/477742 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3450 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154861.pdf [firstpage_image] =>[orig_patent_app_number] => 477742 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/477742
Method and apparatus for built-in self-test of smart memories Jun 6, 1995 Issued
Array ( [id] => 3625817 [patent_doc_number] => 05535326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'System and method for logical console verification and feedback' [patent_app_type] => 1 [patent_app_number] => 8/470375 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2150 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535326.pdf [firstpage_image] =>[orig_patent_app_number] => 470375 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/470375
System and method for logical console verification and feedback Jun 5, 1995 Issued
Array ( [id] => 3644615 [patent_doc_number] => 05631909 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-20 [patent_title] => 'Method and apparatus for determining burst errors in an error pattern' [patent_app_type] => 1 [patent_app_number] => 8/454959 [patent_app_country] => US [patent_app_date] => 1995-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4209 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/631/05631909.pdf [firstpage_image] =>[orig_patent_app_number] => 454959 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/454959
Method and apparatus for determining burst errors in an error pattern May 30, 1995 Issued
Array ( [id] => 3705425 [patent_doc_number] => 05596586 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Failure simulation method' [patent_app_type] => 1 [patent_app_number] => 8/448663 [patent_app_country] => US [patent_app_date] => 1995-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 10839 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/596/05596586.pdf [firstpage_image] =>[orig_patent_app_number] => 448663 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/448663
Failure simulation method May 23, 1995 Issued
Array ( [id] => 4100619 [patent_doc_number] => 06055656 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Control register bus access through a standardized test access port' [patent_app_type] => 1 [patent_app_number] => 8/434163 [patent_app_country] => US [patent_app_date] => 1995-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3578 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055656.pdf [firstpage_image] =>[orig_patent_app_number] => 434163 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/434163
Control register bus access through a standardized test access port May 1, 1995 Issued
Array ( [id] => 3599721 [patent_doc_number] => 05553235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-03 [patent_title] => 'System and method for maintaining performance data in a data processing system' [patent_app_type] => 1 [patent_app_number] => 8/434906 [patent_app_country] => US [patent_app_date] => 1995-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 38 [patent_no_of_words] => 47103 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/553/05553235.pdf [firstpage_image] =>[orig_patent_app_number] => 434906 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/434906
System and method for maintaining performance data in a data processing system Apr 30, 1995 Issued
Array ( [id] => 1490317 [patent_doc_number] => 06367046 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Multi-bit error correction system' [patent_app_type] => B1 [patent_app_number] => 08/428812 [patent_app_country] => US [patent_app_date] => 1995-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2829 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/367/06367046.pdf [firstpage_image] =>[orig_patent_app_number] => 08428812 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/428812
Multi-bit error correction system Apr 23, 1995 Issued
08/419213 METHOD AND APPARATUS FOR TESTING LINKS BETWEEN NETWORK SWITCHES Apr 9, 1995 Abandoned
08/415218 METHOD AND APPARATUS FOR CPU FAILURE RECOVERY IN SYMMETRIC MULTI-PROCESSING SYSTEMS Mar 27, 1995 Abandoned
Array ( [id] => 3700192 [patent_doc_number] => 05644699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Memory apparatus and data processor using the same' [patent_app_type] => 1 [patent_app_number] => 8/403558 [patent_app_country] => US [patent_app_date] => 1995-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 25333 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/644/05644699.pdf [firstpage_image] =>[orig_patent_app_number] => 403558 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/403558
Memory apparatus and data processor using the same Mar 12, 1995 Issued
Array ( [id] => 3733980 [patent_doc_number] => 05701305 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Error recovery in a network having cascaded hubs' [patent_app_type] => 1 [patent_app_number] => 8/397827 [patent_app_country] => US [patent_app_date] => 1995-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8805 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/701/05701305.pdf [firstpage_image] =>[orig_patent_app_number] => 397827 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/397827
Error recovery in a network having cascaded hubs Mar 2, 1995 Issued
Array ( [id] => 3704524 [patent_doc_number] => 05661736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Multiple use timer and method for pulse width generation, echo failure detection, and receive pulse width measurement' [patent_app_type] => 1 [patent_app_number] => 8/395591 [patent_app_country] => US [patent_app_date] => 1995-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2734 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661736.pdf [firstpage_image] =>[orig_patent_app_number] => 395591 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/395591
Multiple use timer and method for pulse width generation, echo failure detection, and receive pulse width measurement Feb 27, 1995 Issued
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