| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3454781
[patent_doc_number] => 05467468
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-14
[patent_title] => 'Semiconductor memory device having built-in test circuits selectively activated by decoder circuit'
[patent_app_type] => 1
[patent_app_number] => 8/022622
[patent_app_country] => US
[patent_app_date] => 1993-02-25
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[pdf_file] => patents/05/467/05467468.pdf
[firstpage_image] =>[orig_patent_app_number] => 022622
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/022622 | Semiconductor memory device having built-in test circuits selectively activated by decoder circuit | Feb 24, 1993 | Issued |
Array
(
[id] => 3104499
[patent_doc_number] => 05369643
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-29
[patent_title] => 'Method and apparatus for mapping test signals of an integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/010422
[patent_app_country] => US
[patent_app_date] => 1993-01-28
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[pdf_file] => patents/05/369/05369643.pdf
[firstpage_image] =>[orig_patent_app_number] => 010422
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/010422 | Method and apparatus for mapping test signals of an integrated circuit | Jan 27, 1993 | Issued |
Array
(
[id] => 3791927
[patent_doc_number] => 05757824
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-26
[patent_title] => 'Code error correction apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/008292
[patent_app_country] => US
[patent_app_date] => 1993-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[patent_words_short_claim] => 414
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[pdf_file] => patents/05/757/05757824.pdf
[firstpage_image] =>[orig_patent_app_number] => 008292
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/008292 | Code error correction apparatus | Jan 24, 1993 | Issued |
| 08/004932 | ELECTRONIC APPARATUS AND METHOD FOR PATCHING A FIXED INFORMATION | Jan 14, 1993 | Abandoned |
Array
(
[id] => 3539456
[patent_doc_number] => 05528755
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-18
[patent_title] => 'Invalid data detection, recording and nullification'
[patent_app_type] => 1
[patent_app_number] => 7/995092
[patent_app_country] => US
[patent_app_date] => 1992-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 6122
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[pdf_file] => patents/05/528/05528755.pdf
[firstpage_image] =>[orig_patent_app_number] => 995092
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/995092 | Invalid data detection, recording and nullification | Dec 21, 1992 | Issued |
Array
(
[id] => 3130203
[patent_doc_number] => 05450426
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-09-12
[patent_title] => 'Continuous error detection using duplicate core memory cells'
[patent_app_type] => 1
[patent_app_number] => 7/993122
[patent_app_country] => US
[patent_app_date] => 1992-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/450/05450426.pdf
[firstpage_image] =>[orig_patent_app_number] => 993122
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/993122 | Continuous error detection using duplicate core memory cells | Dec 17, 1992 | Issued |
Array
(
[id] => 3563789
[patent_doc_number] => 05572663
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-05
[patent_title] => 'Highly reliable information processor system'
[patent_app_type] => 1
[patent_app_number] => 7/992642
[patent_app_country] => US
[patent_app_date] => 1992-12-18
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/572/05572663.pdf
[firstpage_image] =>[orig_patent_app_number] => 992642
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/992642 | Highly reliable information processor system | Dec 17, 1992 | Issued |
Array
(
[id] => 3707171
[patent_doc_number] => 05680541
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-21
[patent_title] => 'Diagnosing method and apparatus'
[patent_app_type] => 1
[patent_app_number] => 7/991092
[patent_app_country] => US
[patent_app_date] => 1992-12-15
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/680/05680541.pdf
[firstpage_image] =>[orig_patent_app_number] => 991092
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/991092 | Diagnosing method and apparatus | Dec 14, 1992 | Issued |
Array
(
[id] => 3458378
[patent_doc_number] => 05421005
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-30
[patent_title] => 'Alternate DRAM refresh controlled by signal period detector'
[patent_app_type] => 1
[patent_app_number] => 7/984358
[patent_app_country] => US
[patent_app_date] => 1992-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1929
[patent_no_of_claims] => 20
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[patent_words_short_claim] => 138
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/421/05421005.pdf
[firstpage_image] =>[orig_patent_app_number] => 984358
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/984358 | Alternate DRAM refresh controlled by signal period detector | Dec 1, 1992 | Issued |
| 07/979302 | SYSTEM FOR TESTING INSTRUCTION QUEUE CIRCUIT AND CENTRAL PROCESSING UNIT HAVING THE SYSTEM | Nov 19, 1992 | Abandoned |
| 07/978752 | PRINTED CIRCUIT BOARD FAULT INJECTION CIRCUIT | Nov 18, 1992 | Abandoned |
| 07/975432 | PARITY CHECKING SYSTEM WITH REDUCED USAGE OF I/O PINS | Nov 11, 1992 | Abandoned |
| 07/965982 | SYSTEM AND METHOD FOR MAINTAINING PERFORMANCE DATA IN A DATA PROCESSING SYSTEM | Oct 22, 1992 | Abandoned |
Array
(
[id] => 3845873
[patent_doc_number] => 05761214
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Method for testing integrated circuit devices'
[patent_app_type] => 1
[patent_app_number] => 7/962952
[patent_app_country] => US
[patent_app_date] => 1992-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/05/761/05761214.pdf
[firstpage_image] =>[orig_patent_app_number] => 962952
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/962952 | Method for testing integrated circuit devices | Oct 15, 1992 | Issued |
| 07/956842 | TRANSMISSION CIRCUIT FOR TRANSMITTING FIXED -LENGTH DATA | Oct 1, 1992 | Abandoned |
| 07/950292 | POWER EFFICIENT RAM DISK AND A METHOD OF EMULATING A ROTATING MEMORY DEVICE | Sep 23, 1992 | Abandoned |
| 07/950842 | MULTI-BIT ERROR CORRECTION SYSTEM | Sep 22, 1992 | Abandoned |
Array
(
[id] => 3501656
[patent_doc_number] => 05471609
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-28
[patent_title] => 'Method for identifying a system holding a `Reserve`'
[patent_app_type] => 1
[patent_app_number] => 7/949282
[patent_app_country] => US
[patent_app_date] => 1992-09-22
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/471/05471609.pdf
[firstpage_image] =>[orig_patent_app_number] => 949282
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/949282 | Method for identifying a system holding a `Reserve` | Sep 21, 1992 | Issued |
Array
(
[id] => 3458349
[patent_doc_number] => 05421003
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-30
[patent_title] => 'Disk storage system with fault tolerant media maintenance'
[patent_app_type] => 1
[patent_app_number] => 7/946982
[patent_app_country] => US
[patent_app_date] => 1992-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
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[pdf_file] => patents/05/421/05421003.pdf
[firstpage_image] =>[orig_patent_app_number] => 946982
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/946982 | Disk storage system with fault tolerant media maintenance | Sep 16, 1992 | Issued |
| 07/946502 | METHOD AND APPARATUS FOR BUILT-IN SELF-TEST OF SMART MEMORIES | Sep 16, 1992 | Abandoned |