Search

Christopher A. Bartels

Examiner (ID: 18414, Phone: (571)270-3182 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2184
Total Applications
586
Issued Applications
352
Pending Applications
73
Abandoned Applications
185

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19451191 [patent_doc_number] => 20240311321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => MULTI-CORE SYSTEM AND READING METHOD [patent_app_type] => utility [patent_app_number] => 18/437924 [patent_app_country] => US [patent_app_date] => 2024-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5230 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18437924 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/437924
MULTI-CORE SYSTEM AND READING METHOD Feb 8, 2024 Pending
Array ( [id] => 19334432 [patent_doc_number] => 20240248862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR HARDWARE CONTROL OF PROCESSOR PERFORMANCE LEVELS [patent_app_type] => utility [patent_app_number] => 18/424010 [patent_app_country] => US [patent_app_date] => 2024-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20253 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18424010 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/424010
APPARATUSES, METHODS, AND SYSTEMS FOR HARDWARE CONTROL OF PROCESSOR PERFORMANCE LEVELS Jan 25, 2024 Pending
Array ( [id] => 19334439 [patent_doc_number] => 20240248869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => METHOD AND APPARATUS WITH PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) DATA TRANSMISSION [patent_app_type] => utility [patent_app_number] => 18/416093 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18416093 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/416093
METHOD AND APPARATUS WITH PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) DATA TRANSMISSION Jan 17, 2024 Pending
Array ( [id] => 19686433 [patent_doc_number] => 20250004978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => DEVICE FOR MONITORING INTER-INTEGRATED CIRCUIT BUS [patent_app_type] => utility [patent_app_number] => 18/537242 [patent_app_country] => US [patent_app_date] => 2023-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18537242 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/537242
DEVICE FOR MONITORING INTER-INTEGRATED CIRCUIT BUS Dec 11, 2023 Pending
Array ( [id] => 19686433 [patent_doc_number] => 20250004978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => DEVICE FOR MONITORING INTER-INTEGRATED CIRCUIT BUS [patent_app_type] => utility [patent_app_number] => 18/537242 [patent_app_country] => US [patent_app_date] => 2023-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18537242 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/537242
DEVICE FOR MONITORING INTER-INTEGRATED CIRCUIT BUS Dec 11, 2023 Pending
Array ( [id] => 19686433 [patent_doc_number] => 20250004978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => DEVICE FOR MONITORING INTER-INTEGRATED CIRCUIT BUS [patent_app_type] => utility [patent_app_number] => 18/537242 [patent_app_country] => US [patent_app_date] => 2023-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18537242 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/537242
DEVICE FOR MONITORING INTER-INTEGRATED CIRCUIT BUS Dec 11, 2023 Pending
Array ( [id] => 20043323 [patent_doc_number] => 20250181545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => Serial Peripheral Interface Control Method [patent_app_type] => utility [patent_app_number] => 18/527837 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18527837 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/527837
Serial Peripheral Interface Control Method Dec 3, 2023 Pending
Array ( [id] => 19711562 [patent_doc_number] => 20250021704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => METHODS AND APPARATUS TO PREVENT A FALSE DISCONNECTION IN UNIVERSAL SERIAL BUS DEVICES [patent_app_type] => utility [patent_app_number] => 18/523590 [patent_app_country] => US [patent_app_date] => 2023-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18523590 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/523590
METHODS AND APPARATUS TO PREVENT A FALSE DISCONNECTION IN UNIVERSAL SERIAL BUS DEVICES Nov 28, 2023 Pending
Array ( [id] => 20000812 [patent_doc_number] => 20250139034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => PROBATION OF DIRECT MEMORY ACCESS DEVICE USED FOR DIRECT DEVICE ASSIGNMENT [patent_app_type] => utility [patent_app_number] => 18/499028 [patent_app_country] => US [patent_app_date] => 2023-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3283 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18499028 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/499028
PROBATION OF DIRECT MEMORY ACCESS DEVICE USED FOR DIRECT DEVICE ASSIGNMENT Oct 30, 2023 Pending
Array ( [id] => 19159773 [patent_doc_number] => 20240152480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => DAISY-CHAINED SERIAL PERIPHERAL INTERFACE [patent_app_type] => utility [patent_app_number] => 18/384962 [patent_app_country] => US [patent_app_date] => 2023-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18384962 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/384962
DAISY-CHAINED SERIAL PERIPHERAL INTERFACE Oct 29, 2023 Pending
Array ( [id] => 19320302 [patent_doc_number] => 20240241846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => DIRECT MEMORY ACCESS DEVICE AND DATA PROCESSING SYSTEM USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/494388 [patent_app_country] => US [patent_app_date] => 2023-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3735 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18494388 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/494388
DIRECT MEMORY ACCESS DEVICE AND DATA PROCESSING SYSTEM USING THE SAME Oct 24, 2023 Pending
Array ( [id] => 19878645 [patent_doc_number] => 20250110902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => PROCESSORS EMPLOYING DEFAULT TAGS FOR WRITES TO MEMORY FROM DEVICES NOT COMPLIANT WITH A MEMORY TAGGING EXTENSION AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 18/478645 [patent_app_country] => US [patent_app_date] => 2023-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6742 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18478645 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/478645
PROCESSORS EMPLOYING DEFAULT TAGS FOR WRITES TO MEMORY FROM DEVICES NOT COMPLIANT WITH A MEMORY TAGGING EXTENSION AND RELATED METHODS Sep 28, 2023 Pending
Array ( [id] => 19303528 [patent_doc_number] => 20240232108 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => DYNAMIC DMA BUFFER MANAGEMENT [patent_app_type] => utility [patent_app_number] => 18/373159 [patent_app_country] => US [patent_app_date] => 2023-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3630 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18373159 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/373159
Dynamic DMA buffer management Sep 25, 2023 Issued
Array ( [id] => 19303528 [patent_doc_number] => 20240232108 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => DYNAMIC DMA BUFFER MANAGEMENT [patent_app_type] => utility [patent_app_number] => 18/373159 [patent_app_country] => US [patent_app_date] => 2023-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3630 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18373159 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/373159
Dynamic DMA buffer management Sep 25, 2023 Issued
Array ( [id] => 18881458 [patent_doc_number] => 20240004827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => USB DEVICE [patent_app_type] => utility [patent_app_number] => 18/464727 [patent_app_country] => US [patent_app_date] => 2023-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18464727 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/464727
USB DEVICE Sep 10, 2023 Pending
Array ( [id] => 18881458 [patent_doc_number] => 20240004827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => USB DEVICE [patent_app_type] => utility [patent_app_number] => 18/464727 [patent_app_country] => US [patent_app_date] => 2023-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18464727 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/464727
USB DEVICE Sep 10, 2023 Pending
Array ( [id] => 19819246 [patent_doc_number] => 20250077453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => HMB Random and Sequential Access Coherency Approach [patent_app_type] => utility [patent_app_number] => 18/461777 [patent_app_country] => US [patent_app_date] => 2023-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6453 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18461777 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/461777
HMB Random and Sequential Access Coherency Approach Sep 5, 2023 Pending
Array ( [id] => 19144614 [patent_doc_number] => 20240143531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => MEMORY SYSTEM AND METHOD OF OPERATING CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/458249 [patent_app_country] => US [patent_app_date] => 2023-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13680 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18458249 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/458249
MEMORY SYSTEM AND METHOD OF OPERATING CONTROLLER Aug 29, 2023 Pending
Array ( [id] => 19391524 [patent_doc_number] => 20240281394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => PROCESSOR EVENT MANAGER [patent_app_type] => utility [patent_app_number] => 18/458369 [patent_app_country] => US [patent_app_date] => 2023-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12960 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18458369 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/458369
PROCESSOR EVENT MANAGER Aug 29, 2023 Pending
Array ( [id] => 19772103 [patent_doc_number] => 20250053529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => STRAIN RELIEF FOR FLOATING CARD ELECTROMECHANICAL CONNECTOR [patent_app_type] => utility [patent_app_number] => 18/448359 [patent_app_country] => US [patent_app_date] => 2023-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3131 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18448359 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/448359
STRAIN RELIEF FOR FLOATING CARD ELECTROMECHANICAL CONNECTOR Aug 10, 2023 Pending
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