Search

Christopher A. Flory

Examiner (ID: 408, Phone: (571)270-5305 , Office: P/3762 )

Most Active Art Unit
3762
Art Unit(s)
3762, 3792
Total Applications
796
Issued Applications
569
Pending Applications
18
Abandoned Applications
216

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11966843 [patent_doc_number] => 20170270996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'SEMICONDUCTOR MEMORY DEIVCE AND ACCESSING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/232823 [patent_app_country] => US [patent_app_date] => 2016-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 7226 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15232823 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/232823
SEMICONDUCTOR MEMORY DEIVCE AND ACCESSING METHOD THEREOF Aug 9, 2016 Abandoned
Array ( [id] => 12953083 [patent_doc_number] => 09837167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-05 [patent_title] => Method for operating storage device changing operation condition depending on data reliability [patent_app_type] => utility [patent_app_number] => 15/227945 [patent_app_country] => US [patent_app_date] => 2016-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 9203 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15227945 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/227945
Method for operating storage device changing operation condition depending on data reliability Aug 2, 2016 Issued
Array ( [id] => 12195335 [patent_doc_number] => 09899069 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-20 [patent_title] => 'Adaptable sense circuitry and method for read-only memory' [patent_app_type] => utility [patent_app_number] => 15/223213 [patent_app_country] => US [patent_app_date] => 2016-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5693 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15223213 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/223213
Adaptable sense circuitry and method for read-only memory Jul 28, 2016 Issued
Array ( [id] => 11860748 [patent_doc_number] => 09740431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Memory controller and method for interleaving DRAM and MRAM accesses' [patent_app_type] => utility [patent_app_number] => 15/212271 [patent_app_country] => US [patent_app_date] => 2016-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7827 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15212271 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/212271
Memory controller and method for interleaving DRAM and MRAM accesses Jul 16, 2016 Issued
Array ( [id] => 11680030 [patent_doc_number] => 09678558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Memory system and method for power management for reducing a variable credit value by a computed consumed energy value for each corresponding updated cycle' [patent_app_type] => utility [patent_app_number] => 15/207221 [patent_app_country] => US [patent_app_date] => 2016-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 11792 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15207221 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/207221
Memory system and method for power management for reducing a variable credit value by a computed consumed energy value for each corresponding updated cycle Jul 10, 2016 Issued
Array ( [id] => 11838752 [patent_doc_number] => 20170220472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'MEMORY SYSTEM AND OPERATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/204401 [patent_app_country] => US [patent_app_date] => 2016-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 20674 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15204401 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/204401
Memory system for reducing program preparation operation time and operation method thereof Jul 6, 2016 Issued
Array ( [id] => 11125118 [patent_doc_number] => 20160322092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'MAGNETIC RANDOM ACCESS MEMORY CELL WITH A DUAL JUNCTION FOR TERNARY CONTENT ADDRESSABLE MEMORY APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 15/190499 [patent_app_country] => US [patent_app_date] => 2016-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3491 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15190499 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/190499
Magnetic random access memory cell with a dual junction for ternary content addressable memory applications Jun 22, 2016 Issued
Array ( [id] => 11659918 [patent_doc_number] => 09672929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-06 [patent_title] => 'Semiconductor memory in which source line voltage is applied during a read operation' [patent_app_type] => utility [patent_app_number] => 15/174114 [patent_app_country] => US [patent_app_date] => 2016-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 12593 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15174114 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/174114
Semiconductor memory in which source line voltage is applied during a read operation Jun 5, 2016 Issued
Array ( [id] => 11725029 [patent_doc_number] => 09697890 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-04 [patent_title] => 'Memory and interface circuit for bit line of memory' [patent_app_type] => utility [patent_app_number] => 15/170092 [patent_app_country] => US [patent_app_date] => 2016-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6941 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15170092 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/170092
Memory and interface circuit for bit line of memory May 31, 2016 Issued
Array ( [id] => 11079064 [patent_doc_number] => 20160276028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'MEMORY DEVICES AND RELATED METHOD INCORPORATING DIFFERENT BIASING SCHEMES' [patent_app_type] => utility [patent_app_number] => 15/165800 [patent_app_country] => US [patent_app_date] => 2016-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6170 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15165800 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/165800
Semiconductor memory devices including a memory array and related method incorporating different biasing schemes May 25, 2016 Issued
Array ( [id] => 11475264 [patent_doc_number] => 20170062047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'DRIVING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/156921 [patent_app_country] => US [patent_app_date] => 2016-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3127 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15156921 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/156921
Driving circuit with adjustable termination resistor May 16, 2016 Issued
Array ( [id] => 11446091 [patent_doc_number] => 20170047112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'DESIGN STRUCTURE FOR REDUCING PRE-CHARGE VOLTAGE FOR STATIC RANDOM-ACCESS MEMORY ARRAYS' [patent_app_type] => utility [patent_app_number] => 15/155236 [patent_app_country] => US [patent_app_date] => 2016-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8947 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15155236 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/155236
Structure for reducing pre-charge voltage for static random-access memory arrays May 15, 2016 Issued
Array ( [id] => 11445444 [patent_doc_number] => 20170046465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'DESIGN STRUCTURE FOR REDUCING PRE-CHARGE VOLTAGE FOR STATIC RANDOM-ACCESS MEMORY ARRAYS' [patent_app_type] => utility [patent_app_number] => 15/155246 [patent_app_country] => US [patent_app_date] => 2016-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8947 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15155246 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/155246
Structure for reducing pre-charge voltage for static random-access memory arrays May 15, 2016 Issued
Array ( [id] => 11446090 [patent_doc_number] => 20170047111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'DESIGN STRUCTURE FOR REDUCING PRE-CHARGE VOLTAGE FOR STATIC RANDOM-ACCESS MEMORY ARRAYS' [patent_app_type] => utility [patent_app_number] => 15/155223 [patent_app_country] => US [patent_app_date] => 2016-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8947 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15155223 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/155223
Structure for reducing pre-charge voltage for static random-access memory arrays May 15, 2016 Issued
Array ( [id] => 13280975 [patent_doc_number] => 10152069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => System and method for controlling a voltage unbalance in a low-voltage direct current distribution system [patent_app_type] => utility [patent_app_number] => 15/053007 [patent_app_country] => US [patent_app_date] => 2016-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6826 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15053007 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/053007
System and method for controlling a voltage unbalance in a low-voltage direct current distribution system Apr 28, 2016 Issued
Array ( [id] => 11043305 [patent_doc_number] => 20160240261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/137222 [patent_app_country] => US [patent_app_date] => 2016-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 12022 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15137222 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/137222
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE Apr 24, 2016 Abandoned
Array ( [id] => 11043278 [patent_doc_number] => 20160240234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'SEMICONDUCTOR APPARATUS CONFIGURED TO MANAGE AN OPERATION TIMING MARGIN' [patent_app_type] => utility [patent_app_number] => 15/137121 [patent_app_country] => US [patent_app_date] => 2016-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7044 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15137121 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/137121
Semiconductor apparatus configured to control data output timing Apr 24, 2016 Issued
Array ( [id] => 12355293 [patent_doc_number] => 09953943 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-24 [patent_title] => Semiconductor apparatus having multiple ranks with noise elimination [patent_app_type] => utility [patent_app_number] => 15/137269 [patent_app_country] => US [patent_app_date] => 2016-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4486 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15137269 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/137269
Semiconductor apparatus having multiple ranks with noise elimination Apr 24, 2016 Issued
Array ( [id] => 11020080 [patent_doc_number] => 20160217034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'READING AND WRITING TO NAND FLASH MEMORIES USING CHARGE CONSTRAINED CODES' [patent_app_type] => utility [patent_app_number] => 15/092110 [patent_app_country] => US [patent_app_date] => 2016-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 12262 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15092110 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/092110
Reading and writing to NAND flash memories using charge constrained codes Apr 5, 2016 Issued
Array ( [id] => 11373685 [patent_doc_number] => 09542980 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-10 [patent_title] => 'Sense amplifier with mini-gap architecture and parallel interconnect' [patent_app_type] => utility [patent_app_number] => 15/083303 [patent_app_country] => US [patent_app_date] => 2016-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2176 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15083303 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/083303
Sense amplifier with mini-gap architecture and parallel interconnect Mar 28, 2016 Issued
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