Search

Christopher A. Flory

Examiner (ID: 408, Phone: (571)270-5305 , Office: P/3762 )

Most Active Art Unit
3762
Art Unit(s)
3762, 3792
Total Applications
796
Issued Applications
569
Pending Applications
18
Abandoned Applications
216

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17120435 [patent_doc_number] => 11131562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => Pedestrian pace estimation with pace change updating [patent_app_type] => utility [patent_app_number] => 14/712871 [patent_app_country] => US [patent_app_date] => 2015-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6865 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14712871 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/712871
Pedestrian pace estimation with pace change updating May 13, 2015 Issued
Array ( [id] => 11307387 [patent_doc_number] => 09514790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-06 [patent_title] => 'Data transmission circuit' [patent_app_type] => utility [patent_app_number] => 14/711045 [patent_app_country] => US [patent_app_date] => 2015-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9987 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14711045 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/711045
Data transmission circuit May 12, 2015 Issued
Array ( [id] => 11787350 [patent_doc_number] => 09396805 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-19 [patent_title] => 'Nonvolatile memory system with improved signal transmission and reception characteristics and method of operating the same' [patent_app_type] => utility [patent_app_number] => 14/711643 [patent_app_country] => US [patent_app_date] => 2015-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 23 [patent_no_of_words] => 9758 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14711643 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/711643
Nonvolatile memory system with improved signal transmission and reception characteristics and method of operating the same May 12, 2015 Issued
Array ( [id] => 10350694 [patent_doc_number] => 20150235699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'APPARATUSES INCLUDING CROSS POINT MEMORY ARRAYS AND BIASING SCHEMES' [patent_app_type] => utility [patent_app_number] => 14/702330 [patent_app_country] => US [patent_app_date] => 2015-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6155 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14702330 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/702330
Apparatuses including cross point memory arrays and biasing schemes Apr 30, 2015 Issued
Array ( [id] => 10425887 [patent_doc_number] => 20150310898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'SYSTEM AND METHOD FOR PROVIDING A CONFIGURABLE TIMING CONTROL FOR A MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/694487 [patent_app_country] => US [patent_app_date] => 2015-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12317 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14694487 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/694487
SYSTEM AND METHOD FOR PROVIDING A CONFIGURABLE TIMING CONTROL FOR A MEMORY SYSTEM Apr 22, 2015 Abandoned
Array ( [id] => 10576810 [patent_doc_number] => 09299460 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-29 [patent_title] => 'Data structure of defective address information and defective address information encoding method for memory array' [patent_app_type] => utility [patent_app_number] => 14/690859 [patent_app_country] => US [patent_app_date] => 2015-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6259 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14690859 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/690859
Data structure of defective address information and defective address information encoding method for memory array Apr 19, 2015 Issued
Array ( [id] => 11125117 [patent_doc_number] => 20160322091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'MAGNETIC TUNNEL JUNCTION SWITCHING ASSISTED BY TEMPERATURE-GRADIENT INDUCED SPIN TORQUE' [patent_app_type] => utility [patent_app_number] => 14/700015 [patent_app_country] => US [patent_app_date] => 2015-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 7377 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14700015 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/700015
Magnetic tunnel junction switching assisted by temperature-gradient induced spin torque Apr 18, 2015 Issued
Array ( [id] => 10336373 [patent_doc_number] => 20150221378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-06 [patent_title] => 'PROGRAM AND READ TRIM SETTING' [patent_app_type] => utility [patent_app_number] => 14/688149 [patent_app_country] => US [patent_app_date] => 2015-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3274 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14688149 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/688149
Program and read trim setting Apr 15, 2015 Issued
Array ( [id] => 10544314 [patent_doc_number] => 09269446 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-02-23 [patent_title] => 'Methods to improve programming of slow cells' [patent_app_type] => utility [patent_app_number] => 14/681653 [patent_app_country] => US [patent_app_date] => 2015-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 10711 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14681653 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/681653
Methods to improve programming of slow cells Apr 7, 2015 Issued
Array ( [id] => 10328879 [patent_doc_number] => 20150213883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'TESTING SIGNAL DEVELOPMENT ON A BIT LINE IN AN SRAM' [patent_app_type] => utility [patent_app_number] => 14/679644 [patent_app_country] => US [patent_app_date] => 2015-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4190 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14679644 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/679644
TESTING SIGNAL DEVELOPMENT ON A BIT LINE IN AN SRAM Apr 5, 2015 Abandoned
Array ( [id] => 10576743 [patent_doc_number] => 09299393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-29 [patent_title] => 'Memory device and semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/679103 [patent_app_country] => US [patent_app_date] => 2015-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 59 [patent_no_of_words] => 27359 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14679103 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/679103
Memory device and semiconductor device Apr 5, 2015 Issued
Array ( [id] => 10687408 [patent_doc_number] => 20160033553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'INTELLIGENT ELECTRICAL CIRCUIT DIGITAL AMPERAGE DISPLAY INTERFACE' [patent_app_type] => utility [patent_app_number] => 14/675882 [patent_app_country] => US [patent_app_date] => 2015-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2508 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14675882 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/675882
INTELLIGENT ELECTRICAL CIRCUIT DIGITAL AMPERAGE DISPLAY INTERFACE Mar 31, 2015 Abandoned
Array ( [id] => 11096278 [patent_doc_number] => 20160293247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'Read-Write Contention Circuitry' [patent_app_type] => utility [patent_app_number] => 14/675687 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11443 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14675687 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/675687
Read-write contention circuitry Mar 30, 2015 Issued
Array ( [id] => 10563274 [patent_doc_number] => 09286955 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-15 [patent_title] => 'Semiconductor memory device having calibration circuitry for dual-gate transistors associated with a memory array' [patent_app_type] => utility [patent_app_number] => 14/668863 [patent_app_country] => US [patent_app_date] => 2015-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10045 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14668863 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/668863
Semiconductor memory device having calibration circuitry for dual-gate transistors associated with a memory array Mar 24, 2015 Issued
Array ( [id] => 10384993 [patent_doc_number] => 20150270001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'MAGNETIC RANDOM ACCESS MEMORY CELL WITH A DUAL JUNCTION FOR TERNARY CONTENT ADDRESSABLE MEMORY APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 14/665459 [patent_app_country] => US [patent_app_date] => 2015-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3509 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14665459 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/665459
Magnetic random access memory cell with a dual junction for ternary content addressable memory applications Mar 22, 2015 Issued
Array ( [id] => 10645099 [patent_doc_number] => 09361972 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-06-07 [patent_title] => 'Charge level maintenance in a memory' [patent_app_type] => utility [patent_app_number] => 14/664617 [patent_app_country] => US [patent_app_date] => 2015-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10458 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14664617 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/664617
Charge level maintenance in a memory Mar 19, 2015 Issued
Array ( [id] => 10309217 [patent_doc_number] => 20150194218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-09 [patent_title] => 'MEMORY CELL SENSING' [patent_app_type] => utility [patent_app_number] => 14/663179 [patent_app_country] => US [patent_app_date] => 2015-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11388 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14663179 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/663179
Memory cell sensing Mar 18, 2015 Issued
Array ( [id] => 10779794 [patent_doc_number] => 20160125950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'DATA STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 14/642083 [patent_app_country] => US [patent_app_date] => 2015-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3255 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14642083 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/642083
Data storage device including nonvolatile memory in which on/off state of power source voltage is controlled Mar 8, 2015 Issued
Array ( [id] => 11050595 [patent_doc_number] => 20160247554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'STATIC RANDOM-ACCESS MEMORY (SRAM) SENSOR' [patent_app_type] => utility [patent_app_number] => 14/631603 [patent_app_country] => US [patent_app_date] => 2015-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8954 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14631603 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/631603
Static random-access memory (SRAM) sensor for bias temperature instability Feb 24, 2015 Issued
Array ( [id] => 11043281 [patent_doc_number] => 20160240237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'ADJUSTING RESISTIVE MEMORY WRITE DRIVER STRENGTH BASED ON A MIMIC RESISTIVE MEMORY WRITE OPERATION' [patent_app_type] => utility [patent_app_number] => 14/620487 [patent_app_country] => US [patent_app_date] => 2015-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10306 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14620487 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/620487
Adjusting resistive memory write driver strength based on a mimic resistive memory write operation Feb 11, 2015 Issued
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