Christopher A. Flory

Array ( [id] => 8665992 [patent_doc_number] => 08379460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Trim circuit and semiconductor memory device comprising same' [patent_app_type] => utility [patent_app_number] => 12/912001 [patent_app_country] => US [patent_app_date] => 2010-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 7806 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12912001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8676998 [patent_doc_number] => 08385120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Method of programming a nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 12/910063 [patent_app_country] => US [patent_app_date] => 2010-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8488 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12910063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4615311 [patent_doc_number] => 07990758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'Power saving semiconductor memory' [patent_app_type] => utility [patent_app_number] => 12/901930 [patent_app_country] => US [patent_app_date] => 2010-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9495 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/990/07990758.pdf [firstpage_image] =>[orig_patent_app_number] => 12901930 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7541602 [patent_doc_number] => 08059450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-15 [patent_title] => 'Write verify method for resistive random access memory' [patent_app_type] => utility [patent_app_number] => 12/899646 [patent_app_country] => US [patent_app_date] => 2010-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/059/08059450.pdf [firstpage_image] =>[orig_patent_app_number] => 12899646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7719087 [patent_doc_number] => 20120008422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/881813 [patent_app_country] => US [patent_app_date] => 2010-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4569 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20120008422.pdf [firstpage_image] =>[orig_patent_app_number] => 12881813 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5974434 [patent_doc_number] => 20110069532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-24 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/876637 [patent_app_country] => US [patent_app_date] => 2010-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20110069532.pdf [firstpage_image] =>[orig_patent_app_number] => 12876637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8750792 [patent_doc_number] => 08416631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Internal voltage generator circuit and semiconductor memory device using the same' [patent_app_type] => utility [patent_app_number] => 12/874299 [patent_app_country] => US [patent_app_date] => 2010-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8893 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12874299 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6086594 [patent_doc_number] => 20110216577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-08 [patent_title] => 'VARIABLE RESISTANCE NONVOLATILE STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 13/126257 [patent_app_country] => US [patent_app_date] => 2010-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 21497 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20110216577.pdf [firstpage_image] =>[orig_patent_app_number] => 13126257 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7783186 [patent_doc_number] => 20120044742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-23 [patent_title] => 'VARIABLE RESISTANCE MEMORY ARRAY ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 12/859981 [patent_app_country] => US [patent_app_date] => 2010-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2962 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20120044742.pdf [firstpage_image] =>[orig_patent_app_number] => 12859981 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7585563 [patent_doc_number] => 20110280073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'NON-VOLATILE STATIC RANDOM ACCESS MEMORY AND OPERATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/853301 [patent_app_country] => US [patent_app_date] => 2010-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8595 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20110280073.pdf [firstpage_image] =>[orig_patent_app_number] => 12853301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8983487 [patent_doc_number] => 08514611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Memory with low voltage mode operation' [patent_app_type] => utility [patent_app_number] => 12/850533 [patent_app_country] => US [patent_app_date] => 2010-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12850533 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6023169 [patent_doc_number] => 20110051495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH NO DECREASE IN READ MARGIN AND METHOD OF READING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/848487 [patent_app_country] => US [patent_app_date] => 2010-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3625 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20110051495.pdf [firstpage_image] =>[orig_patent_app_number] => 12848487 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9693600 [patent_doc_number] => 08824219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-02 [patent_title] => 'Power source circuit and semiconductor memory circuit using the same' [patent_app_type] => utility [patent_app_number] => 12/840223 [patent_app_country] => US [patent_app_date] => 2010-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2495 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12840223 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7730147 [patent_doc_number] => 20120014183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-19 [patent_title] => '3 TRANSISTOR (N/P/N) NON-VOLATILE MEMORY CELL WITHOUT PROGRAM DISTURB' [patent_app_type] => utility [patent_app_number] => 12/837835 [patent_app_country] => US [patent_app_date] => 2010-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2794 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20120014183.pdf [firstpage_image] =>[orig_patent_app_number] => 12837835 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8691532 [patent_doc_number] => 08391063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Method of operating memory cell' [patent_app_type] => utility [patent_app_number] => 12/835075 [patent_app_country] => US [patent_app_date] => 2010-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4637 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12835075 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10525833 [patent_doc_number] => 09252356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Magnetization reversal device, memory element, and magnetic field generation device' [patent_app_type] => utility [patent_app_number] => 13/382801 [patent_app_country] => US [patent_app_date] => 2010-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12331 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13382801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7719115 [patent_doc_number] => 20120008450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'FLEXIBLE MEMORY ARCHITECTURE FOR STATIC POWER REDUCTION AND METHOD OF IMPLEMENTING THE SAME IN AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/831439 [patent_app_country] => US [patent_app_date] => 2010-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2744 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20120008450.pdf [firstpage_image] =>[orig_patent_app_number] => 12831439 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7716533 [patent_doc_number] => 20120006801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'ARC ENERGY REGULATION IN DRAWN ARC FASTENER WELDING PROCESS' [patent_app_type] => utility [patent_app_number] => 12/830764 [patent_app_country] => US [patent_app_date] => 2010-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 4002 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20120006801.pdf [firstpage_image] =>[orig_patent_app_number] => 12830764 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7708906 [patent_doc_number] => 20120002500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'Multi-Voltage Level, Multi-Dynamic Circuit Structure Device' [patent_app_type] => utility [patent_app_number] => 12/828719 [patent_app_country] => US [patent_app_date] => 2010-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6761 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12828719 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9356851 [patent_doc_number] => 08675397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-18 [patent_title] => 'Cell structure for dual-port SRAM' [patent_app_type] => utility [patent_app_number] => 12/823907 [patent_app_country] => US [patent_app_date] => 2010-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9296 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12823907 [rel_patent_id] =>[rel_patent_doc_number] =>)