Search

Christopher A. Flory

Examiner (ID: 408, Phone: (571)270-5305 , Office: P/3762 )

Most Active Art Unit
3762
Art Unit(s)
3762, 3792
Total Applications
796
Issued Applications
569
Pending Applications
18
Abandoned Applications
216

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6564838 [patent_doc_number] => 20100128544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-27 [patent_title] => 'Bit line bridge detecting method in semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/591073 [patent_app_country] => US [patent_app_date] => 2009-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10721 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20100128544.pdf [firstpage_image] =>[orig_patent_app_number] => 12591073 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/591073
Bit line bridge detecting method in semiconductor memory device Nov 5, 2009 Abandoned
Array ( [id] => 8307200 [patent_doc_number] => 08228747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-24 [patent_title] => 'Delay adjustment device, semiconductor device and delay adjustment method' [patent_app_type] => utility [patent_app_number] => 12/588909 [patent_app_country] => US [patent_app_date] => 2009-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7767 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12588909 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/588909
Delay adjustment device, semiconductor device and delay adjustment method Nov 1, 2009 Issued
Array ( [id] => 8167437 [patent_doc_number] => 08174893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'Independent well bias management in a memory device' [patent_app_type] => utility [patent_app_number] => 12/582458 [patent_app_country] => US [patent_app_date] => 2009-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6166 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/174/08174893.pdf [firstpage_image] =>[orig_patent_app_number] => 12582458 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/582458
Independent well bias management in a memory device Oct 19, 2009 Issued
Array ( [id] => 8934072 [patent_doc_number] => 08493782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Memory device and program method thereof' [patent_app_type] => utility [patent_app_number] => 12/580579 [patent_app_country] => US [patent_app_date] => 2009-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 9783 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12580579 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/580579
Memory device and program method thereof Oct 15, 2009 Issued
Array ( [id] => 6123401 [patent_doc_number] => 20110085372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'NON-VOLATILE SRAM CELL THAT INCORPORATES PHASE-CHANGE MEMORY INTO A CMOS PROCESS' [patent_app_type] => utility [patent_app_number] => 12/577631 [patent_app_country] => US [patent_app_date] => 2009-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2205 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20110085372.pdf [firstpage_image] =>[orig_patent_app_number] => 12577631 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/577631
Non-volatile SRAM cell that incorporates phase-change memory into a CMOS process Oct 11, 2009 Issued
Array ( [id] => 6470600 [patent_doc_number] => 20100091596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'SOLID STATE DRIVE SYSTEMS AND METHODS OF REDUCING TEST TIMES OF THE SAME' [patent_app_type] => utility [patent_app_number] => 12/576543 [patent_app_country] => US [patent_app_date] => 2009-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7560 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20100091596.pdf [firstpage_image] =>[orig_patent_app_number] => 12576543 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/576543
Solid state drive systems and methods of reducing test times of the same Oct 8, 2009 Issued
Array ( [id] => 8258792 [patent_doc_number] => 08208301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-26 [patent_title] => 'Nonvolatile memory devices having common bit line structure' [patent_app_type] => utility [patent_app_number] => 12/573239 [patent_app_country] => US [patent_app_date] => 2009-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 8438 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12573239 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/573239
Nonvolatile memory devices having common bit line structure Oct 4, 2009 Issued
Array ( [id] => 9470758 [patent_doc_number] => 08724401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-13 [patent_title] => 'Data stripes and addressing for flash memory devices' [patent_app_type] => utility [patent_app_number] => 12/568729 [patent_app_country] => US [patent_app_date] => 2009-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3196 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12568729 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/568729
Data stripes and addressing for flash memory devices Sep 28, 2009 Issued
Array ( [id] => 6337316 [patent_doc_number] => 20100328986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'MAGNETIC SHIFT REGISTER MEMORY IN STACK STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/565779 [patent_app_country] => US [patent_app_date] => 2009-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5147 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0328/20100328986.pdf [firstpage_image] =>[orig_patent_app_number] => 12565779 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/565779
Magnetic shift register memory in stack structure Sep 23, 2009 Issued
Array ( [id] => 6508031 [patent_doc_number] => 20100202181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/561531 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7371 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20100202181.pdf [firstpage_image] =>[orig_patent_app_number] => 12561531 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561531
SEMICONDUCTOR MEMORY DEVICE Sep 16, 2009 Abandoned
Array ( [id] => 6331880 [patent_doc_number] => 20100246299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'SEMICONDUCTOR STORAGE DEVICE AND REDUNDANCY METHOD' [patent_app_type] => utility [patent_app_number] => 12/559925 [patent_app_country] => US [patent_app_date] => 2009-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9515 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20100246299.pdf [firstpage_image] =>[orig_patent_app_number] => 12559925 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/559925
SEMICONDUCTOR STORAGE DEVICE AND REDUNDANCY METHOD Sep 14, 2009 Abandoned
Array ( [id] => 9650385 [patent_doc_number] => 08804411 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-08-12 [patent_title] => 'Dual mode clock and data scheme for memory programming' [patent_app_type] => utility [patent_app_number] => 12/557723 [patent_app_country] => US [patent_app_date] => 2009-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2006 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12557723 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/557723
Dual mode clock and data scheme for memory programming Sep 10, 2009 Issued
Array ( [id] => 7777303 [patent_doc_number] => 08120981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Semiconductor integrated circuit device with fuse elements and control method therefore' [patent_app_type] => utility [patent_app_number] => 12/555031 [patent_app_country] => US [patent_app_date] => 2009-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5158 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/120/08120981.pdf [firstpage_image] =>[orig_patent_app_number] => 12555031 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/555031
Semiconductor integrated circuit device with fuse elements and control method therefore Sep 7, 2009 Issued
Array ( [id] => 6023177 [patent_doc_number] => 20110051503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'Magnetic Devices and Structures' [patent_app_type] => utility [patent_app_number] => 12/553619 [patent_app_country] => US [patent_app_date] => 2009-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6880 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20110051503.pdf [firstpage_image] =>[orig_patent_app_number] => 12553619 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/553619
Magnetic devices and structures Sep 2, 2009 Issued
Array ( [id] => 8330084 [patent_doc_number] => 08238154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-07 [patent_title] => 'Nonvolatile semiconductor memory with charge storage layers and control gates' [patent_app_type] => utility [patent_app_number] => 12/552563 [patent_app_country] => US [patent_app_date] => 2009-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 16548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12552563 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/552563
Nonvolatile semiconductor memory with charge storage layers and control gates Sep 1, 2009 Issued
Array ( [id] => 8154827 [patent_doc_number] => 08169825 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-05-01 [patent_title] => 'Reliable data storage in analog memory cells subjected to long retention periods' [patent_app_type] => utility [patent_app_number] => 12/551567 [patent_app_country] => US [patent_app_date] => 2009-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 9205 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/169/08169825.pdf [firstpage_image] =>[orig_patent_app_number] => 12551567 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/551567
Reliable data storage in analog memory cells subjected to long retention periods Aug 31, 2009 Issued
Array ( [id] => 6218941 [patent_doc_number] => 20100054036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'Methods of precharging non-volatile memory devices during a programming operation and memory devices programmed thereby' [patent_app_type] => utility [patent_app_number] => 12/583811 [patent_app_country] => US [patent_app_date] => 2009-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 18157 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20100054036.pdf [firstpage_image] =>[orig_patent_app_number] => 12583811 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/583811
Methods of precharging non-volatile memory devices during a programming operation and memory devices programmed thereby Aug 25, 2009 Issued
Array ( [id] => 8726915 [patent_doc_number] => 08406048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-26 [patent_title] => 'Accessing memory using fractional reference voltages' [patent_app_type] => utility [patent_app_number] => 12/535987 [patent_app_country] => US [patent_app_date] => 2009-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8658 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12535987 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/535987
Accessing memory using fractional reference voltages Aug 4, 2009 Issued
Array ( [id] => 4611895 [patent_doc_number] => 07995394 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'Program voltage compensation with word line bias change to suppress charge trapping in memory' [patent_app_type] => utility [patent_app_number] => 12/512181 [patent_app_country] => US [patent_app_date] => 2009-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 28 [patent_no_of_words] => 15708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/995/07995394.pdf [firstpage_image] =>[orig_patent_app_number] => 12512181 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/512181
Program voltage compensation with word line bias change to suppress charge trapping in memory Jul 29, 2009 Issued
Array ( [id] => 9185381 [patent_doc_number] => 08625327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Magnetic random access memory and initializing method for the same' [patent_app_type] => utility [patent_app_number] => 13/054577 [patent_app_country] => US [patent_app_date] => 2009-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 8944 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13054577 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/054577
Magnetic random access memory and initializing method for the same Jul 1, 2009 Issued
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