Search

Christopher A. Flory

Examiner (ID: 408, Phone: (571)270-5305 , Office: P/3762 )

Most Active Art Unit
3762
Art Unit(s)
3762, 3792
Total Applications
796
Issued Applications
569
Pending Applications
18
Abandoned Applications
216

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4635754 [patent_doc_number] => 08014210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-06 [patent_title] => 'Non-volatile memory control circuit' [patent_app_type] => utility [patent_app_number] => 12/480143 [patent_app_country] => US [patent_app_date] => 2009-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2670 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/014/08014210.pdf [firstpage_image] =>[orig_patent_app_number] => 12480143 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/480143
Non-volatile memory control circuit Jun 7, 2009 Issued
Array ( [id] => 6643646 [patent_doc_number] => 20100312999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'INTERNAL PROCESSOR BUFFER' [patent_app_type] => utility [patent_app_number] => 12/478457 [patent_app_country] => US [patent_app_date] => 2009-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6654 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0312/20100312999.pdf [firstpage_image] =>[orig_patent_app_number] => 12478457 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/478457
Internal processor buffer Jun 3, 2009 Issued
Array ( [id] => 6627883 [patent_doc_number] => 20100226166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'MOS capacitor and charge pump with MOS capacitor' [patent_app_type] => utility [patent_app_number] => 12/454121 [patent_app_country] => US [patent_app_date] => 2009-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5408 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20100226166.pdf [firstpage_image] =>[orig_patent_app_number] => 12454121 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/454121
MOS capacitor and charge pump with MOS capacitor May 12, 2009 Abandoned
Array ( [id] => 6577864 [patent_doc_number] => 20100061164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'FAIL-SAFE HIGH SPEED LEVEL SHIFTER FOR WIDE SUPPLY VOLTAGE RANGE' [patent_app_type] => utility [patent_app_number] => 12/464749 [patent_app_country] => US [patent_app_date] => 2009-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5985 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20100061164.pdf [firstpage_image] =>[orig_patent_app_number] => 12464749 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/464749
Fail-safe high speed level shifter for wide supply voltage range May 11, 2009 Issued
Array ( [id] => 6464610 [patent_doc_number] => 20100284219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'MULTIPLE LEVEL PROGRAM VERIFY IN A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/436955 [patent_app_country] => US [patent_app_date] => 2009-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4043 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20100284219.pdf [firstpage_image] =>[orig_patent_app_number] => 12436955 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/436955
Multiple level program verify in a memory device May 6, 2009 Issued
Array ( [id] => 7777286 [patent_doc_number] => 08120972 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Semiconductor memory apparatus and test circuit therefor' [patent_app_type] => utility [patent_app_number] => 12/431131 [patent_app_country] => US [patent_app_date] => 2009-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2998 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/120/08120972.pdf [firstpage_image] =>[orig_patent_app_number] => 12431131 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/431131
Semiconductor memory apparatus and test circuit therefor Apr 27, 2009 Issued
Array ( [id] => 8022507 [patent_doc_number] => 08140769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-20 [patent_title] => 'Data prefetcher' [patent_app_type] => utility [patent_app_number] => 12/426801 [patent_app_country] => US [patent_app_date] => 2009-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 16613 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/140/08140769.pdf [firstpage_image] =>[orig_patent_app_number] => 12426801 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/426801
Data prefetcher Apr 19, 2009 Issued
Array ( [id] => 8149235 [patent_doc_number] => 08166251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-24 [patent_title] => 'Data prefetcher that adjusts prefetch stream length based on confidence' [patent_app_type] => utility [patent_app_number] => 12/426808 [patent_app_country] => US [patent_app_date] => 2009-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 16561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/166/08166251.pdf [firstpage_image] =>[orig_patent_app_number] => 12426808 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/426808
Data prefetcher that adjusts prefetch stream length based on confidence Apr 19, 2009 Issued
Array ( [id] => 6240825 [patent_doc_number] => 20100268885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'SPECIFYING AN ACCESS HINT FOR PREFETCHING LIMITED USE DATA IN A CACHE HIERARCHY' [patent_app_type] => utility [patent_app_number] => 12/424681 [patent_app_country] => US [patent_app_date] => 2009-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3932 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20100268885.pdf [firstpage_image] =>[orig_patent_app_number] => 12424681 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/424681
Specifying an access hint for prefetching limited use data in a cache hierarchy Apr 15, 2009 Issued
Array ( [id] => 7516634 [patent_doc_number] => 08040714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-18 [patent_title] => 'Multilevel nonvolatile memory device using variable resistance' [patent_app_type] => utility [patent_app_number] => 12/423881 [patent_app_country] => US [patent_app_date] => 2009-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6550 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/040/08040714.pdf [firstpage_image] =>[orig_patent_app_number] => 12423881 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/423881
Multilevel nonvolatile memory device using variable resistance Apr 14, 2009 Issued
Array ( [id] => 8219980 [patent_doc_number] => 08195880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Information handling system with immediate scheduling of load operations in a dual-bank cache with dual dispatch into write/read data flow' [patent_app_type] => utility [patent_app_number] => 12/424255 [patent_app_country] => US [patent_app_date] => 2009-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14142 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/195/08195880.pdf [firstpage_image] =>[orig_patent_app_number] => 12424255 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/424255
Information handling system with immediate scheduling of load operations in a dual-bank cache with dual dispatch into write/read data flow Apr 14, 2009 Issued
Array ( [id] => 8022499 [patent_doc_number] => 08140765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-20 [patent_title] => 'Information handling system with immediate scheduling of load operations in a dual-bank cache with single dispatch into write/read data flow' [patent_app_type] => utility [patent_app_number] => 12/424228 [patent_app_country] => US [patent_app_date] => 2009-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14131 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/140/08140765.pdf [firstpage_image] =>[orig_patent_app_number] => 12424228 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/424228
Information handling system with immediate scheduling of load operations in a dual-bank cache with single dispatch into write/read data flow Apr 14, 2009 Issued
Array ( [id] => 7732295 [patent_doc_number] => 08102728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Cache optimizations using multiple threshold voltage transistors' [patent_app_type] => utility [patent_app_number] => 12/419605 [patent_app_country] => US [patent_app_date] => 2009-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8755 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/102/08102728.pdf [firstpage_image] =>[orig_patent_app_number] => 12419605 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/419605
Cache optimizations using multiple threshold voltage transistors Apr 6, 2009 Issued
Array ( [id] => 8593361 [patent_doc_number] => 08351238 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-08 [patent_title] => 'Low-complexity electronic circuits and methods of forming the same' [patent_app_type] => utility [patent_app_number] => 12/417245 [patent_app_country] => US [patent_app_date] => 2009-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5136 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12417245 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/417245
Low-complexity electronic circuits and methods of forming the same Apr 1, 2009 Issued
Array ( [id] => 6331871 [patent_doc_number] => 20100246298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'INTEGRATED CIRCUIT MEMORY HAVING ASSISTED ACCESS AND METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 12/414761 [patent_app_country] => US [patent_app_date] => 2009-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6625 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20100246298.pdf [firstpage_image] =>[orig_patent_app_number] => 12414761 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/414761
Integrated circuit memory having assisted access and method therefor Mar 30, 2009 Issued
Array ( [id] => 7528795 [patent_doc_number] => 08045399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-25 [patent_title] => 'Data output circuit in a semiconductor memory apparatus' [patent_app_type] => utility [patent_app_number] => 12/410579 [patent_app_country] => US [patent_app_date] => 2009-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3186 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/045/08045399.pdf [firstpage_image] =>[orig_patent_app_number] => 12410579 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/410579
Data output circuit in a semiconductor memory apparatus Mar 24, 2009 Issued
Array ( [id] => 7516655 [patent_doc_number] => 08040735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-18 [patent_title] => 'Semiconductor memory device capable of detecting write completion at high speed' [patent_app_type] => utility [patent_app_number] => 12/406385 [patent_app_country] => US [patent_app_date] => 2009-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 8879 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/040/08040735.pdf [firstpage_image] =>[orig_patent_app_number] => 12406385 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/406385
Semiconductor memory device capable of detecting write completion at high speed Mar 17, 2009 Issued
Array ( [id] => 5301853 [patent_doc_number] => 20090296505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'Memory test method and memory test device' [patent_app_type] => utility [patent_app_number] => 12/382485 [patent_app_country] => US [patent_app_date] => 2009-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5944 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20090296505.pdf [firstpage_image] =>[orig_patent_app_number] => 12382485 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/382485
Memory test method and memory test device Mar 16, 2009 Issued
Array ( [id] => 5532115 [patent_doc_number] => 20090231903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'FERROELECTRIC MEMORY AND METHOD FOR TESTING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/404157 [patent_app_country] => US [patent_app_date] => 2009-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 51 [patent_no_of_words] => 15769 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20090231903.pdf [firstpage_image] =>[orig_patent_app_number] => 12404157 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/404157
Ferroelectric memory and method for testing the same Mar 12, 2009 Issued
Array ( [id] => 5478769 [patent_doc_number] => 20090201726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-13 [patent_title] => 'NON-VOLATILE SEMICONDUCTOR STORAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/397369 [patent_app_country] => US [patent_app_date] => 2009-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8935 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20090201726.pdf [firstpage_image] =>[orig_patent_app_number] => 12397369 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/397369
Non-volatile semiconductor storage system Mar 3, 2009 Issued
Menu