Search

Christopher Anthony Daley

Examiner (ID: 14782, Phone: (571)272-3625 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2111, 2185, 2184
Total Applications
1074
Issued Applications
854
Pending Applications
71
Abandoned Applications
175

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19822270 [patent_doc_number] => 20250080477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => DYNAMIC ROUTING FOR ACCELERATED DEEP LEARNING [patent_app_type] => utility [patent_app_number] => 18/945169 [patent_app_country] => US [patent_app_date] => 2024-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 88956 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18945169 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/945169
DYNAMIC ROUTING FOR ACCELERATED DEEP LEARNING Nov 11, 2024 Pending
Array ( [id] => 19802648 [patent_doc_number] => 20250068573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => MEMORY AND OPERATING METHOD THEREOF, MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/943232 [patent_app_country] => US [patent_app_date] => 2024-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10365 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18943232 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/943232
MEMORY AND OPERATING METHOD THEREOF, MEMORY SYSTEM Nov 10, 2024 Pending
Array ( [id] => 20043314 [patent_doc_number] => 20250181536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => CHIPLET WITH ADDRESS REMAPPER BLOCK [patent_app_type] => utility [patent_app_number] => 18/935126 [patent_app_country] => US [patent_app_date] => 2024-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6531 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18935126 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/935126
CHIPLET WITH ADDRESS REMAPPER BLOCK Oct 31, 2024 Pending
Array ( [id] => 20043314 [patent_doc_number] => 20250181536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => CHIPLET WITH ADDRESS REMAPPER BLOCK [patent_app_type] => utility [patent_app_number] => 18/935126 [patent_app_country] => US [patent_app_date] => 2024-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6531 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18935126 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/935126
CHIPLET WITH ADDRESS REMAPPER BLOCK Oct 31, 2024 Pending
Array ( [id] => 19878660 [patent_doc_number] => 20250110917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => MULTI-PROCESSOR DEVICE WITH EXTERNAL INTERFACE FAILOVER [patent_app_type] => utility [patent_app_number] => 18/919053 [patent_app_country] => US [patent_app_date] => 2024-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4795 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18919053 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/919053
MULTI-PROCESSOR DEVICE WITH EXTERNAL INTERFACE FAILOVER Oct 16, 2024 Pending
Array ( [id] => 19748018 [patent_doc_number] => 20250036583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/917560 [patent_app_country] => US [patent_app_date] => 2024-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18917560 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/917560
MEMORY SYSTEM Oct 15, 2024 Pending
Array ( [id] => 19748018 [patent_doc_number] => 20250036583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/917560 [patent_app_country] => US [patent_app_date] => 2024-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18917560 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/917560
MEMORY SYSTEM Oct 15, 2024 Pending
Array ( [id] => 19748023 [patent_doc_number] => 20250036588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => SYSTEM-ON-CHIP AND AN INTERCONNECT BUS INCLUDED IN THE SYSTEM ON CHIP [patent_app_type] => utility [patent_app_number] => 18/915833 [patent_app_country] => US [patent_app_date] => 2024-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18915833 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/915833
SYSTEM-ON-CHIP AND AN INTERCONNECT BUS INCLUDED IN THE SYSTEM ON CHIP Oct 14, 2024 Pending
Array ( [id] => 19819252 [patent_doc_number] => 20250077459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => STACKED DEVICE SYSTEM [patent_app_type] => utility [patent_app_number] => 18/892110 [patent_app_country] => US [patent_app_date] => 2024-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18892110 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/892110
STACKED DEVICE SYSTEM Sep 19, 2024 Pending
Array ( [id] => 19686417 [patent_doc_number] => 20250004962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => DATA BURST SUSPEND MODE USING MULTI-LEVEL SIGNALING [patent_app_type] => utility [patent_app_number] => 18/829713 [patent_app_country] => US [patent_app_date] => 2024-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9390 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18829713 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/829713
DATA BURST SUSPEND MODE USING MULTI-LEVEL SIGNALING Sep 9, 2024 Pending
Array ( [id] => 19635583 [patent_doc_number] => 20240414032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => EQUALIZATION TRAINING METHOD AND APPARATUS, AND SYSTEM [patent_app_type] => utility [patent_app_number] => 18/810900 [patent_app_country] => US [patent_app_date] => 2024-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22077 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18810900 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/810900
EQUALIZATION TRAINING METHOD AND APPARATUS, AND SYSTEM Aug 20, 2024 Pending
Array ( [id] => 19602953 [patent_doc_number] => 20240393833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => NETWORK-CAPABLE DOCKING STATION [patent_app_type] => utility [patent_app_number] => 18/791837 [patent_app_country] => US [patent_app_date] => 2024-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6662 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18791837 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/791837
NETWORK-CAPABLE DOCKING STATION Jul 31, 2024 Pending
Array ( [id] => 20454789 [patent_doc_number] => 12517843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Third party applications for a network-capable docking station [patent_app_type] => utility [patent_app_number] => 18/786104 [patent_app_country] => US [patent_app_date] => 2024-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7188 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18786104 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/786104
Third party applications for a network-capable docking station Jul 25, 2024 Issued
Array ( [id] => 20123360 [patent_doc_number] => 20250238391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => DUAL INTERFACE HIGH-SPEED MEMORY SUBSYSTEM [patent_app_type] => utility [patent_app_number] => 18/783335 [patent_app_country] => US [patent_app_date] => 2024-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18783335 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/783335
DUAL INTERFACE HIGH-SPEED MEMORY SUBSYSTEM Jul 23, 2024 Pending
Array ( [id] => 19558500 [patent_doc_number] => 20240370292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => Automatic Reconfiguration of Network Interface Driver on Network Sensor [patent_app_type] => utility [patent_app_number] => 18/773734 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11993 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18773734 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/773734
Automatic reconfiguration of network interface driver on network sensor host Jul 15, 2024 Issued
Array ( [id] => 20323290 [patent_doc_number] => 20250335378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => STREAMING PROTOCOL FLOW CONTROL FOR DIE-TO-DIE INTERFACES [patent_app_type] => utility [patent_app_number] => 18/765210 [patent_app_country] => US [patent_app_date] => 2024-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10048 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18765210 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/765210
STREAMING PROTOCOL FLOW CONTROL FOR DIE-TO-DIE INTERFACES Jul 4, 2024 Pending
Array ( [id] => 19530370 [patent_doc_number] => 20240354272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => END-TO-END ISOLATION OVER PCIE [patent_app_type] => utility [patent_app_number] => 18/763195 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8441 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763195 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763195
End-to-end isolation over PCIe Jul 2, 2024 Issued
Array ( [id] => 19635574 [patent_doc_number] => 20240414023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => CONTROL ARRANGEMENT FOR A VEHICLE ELECTRICAL SYSTEM [patent_app_type] => utility [patent_app_number] => 18/763421 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7427 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763421 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763421
CONTROL ARRANGEMENT FOR A VEHICLE ELECTRICAL SYSTEM Jul 2, 2024 Pending
Array ( [id] => 19635574 [patent_doc_number] => 20240414023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => CONTROL ARRANGEMENT FOR A VEHICLE ELECTRICAL SYSTEM [patent_app_type] => utility [patent_app_number] => 18/763421 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7427 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763421 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763421
CONTROL ARRANGEMENT FOR A VEHICLE ELECTRICAL SYSTEM Jul 2, 2024 Pending
Array ( [id] => 19530370 [patent_doc_number] => 20240354272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => END-TO-END ISOLATION OVER PCIE [patent_app_type] => utility [patent_app_number] => 18/763195 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8441 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763195 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763195
End-to-end isolation over PCIe Jul 2, 2024 Issued
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